EDN Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.830s	17.393us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.600s	27.160us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.730s	24.190us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.330s	58.050us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.150s	33.693us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.160s	27.981us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.730s	24.190us	1	1	100.00
		edn_csr_aliasing	2.150s	33.693us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.270s	58.192us	1	1	100.00
V2	csrng_commands	edn_genbits	2.270s	58.192us	1	1	100.00
V2	genbits	edn_genbits	2.270s	58.192us	1	1	100.00
V2	interrupts	edn_intr	1.930s	22.692us	1	1	100.00
V2	alerts	edn_alert	2.160s	49.672us	1	1	100.00
V2	errs	edn_err	1.990s	19.229us	1	1	100.00
V2	disable	edn_disable	1.770s	12.959us	1	1	100.00
		edn_disable_auto_req_mode	1.980s	62.768us	1	1	100.00
V2	stress_all	edn_stress_all	5.430s	790.847us	1	1	100.00
V2	intr_test	edn_intr_test	2.150s	11.225us	1	1	100.00
V2	alert_test	edn_alert_test	2.070s	75.848us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.960s	72.267us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.960s	72.267us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.600s	27.160us	1	1	100.00
		edn_csr_rw	1.730s	24.190us	1	1	100.00
		edn_csr_aliasing	2.150s	33.693us	1	1	100.00
		edn_same_csr_outstanding	2.170s	33.371us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.600s	27.160us	1	1	100.00
		edn_csr_rw	1.730s	24.190us	1	1	100.00
		edn_csr_aliasing	2.150s	33.693us	1	1	100.00
		edn_same_csr_outstanding	2.170s	33.371us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.120s	1.121ms	1	1	100.00
		edn_tl_intg_err	3.200s	126.722us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	2.020s	17.504us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.160s	49.672us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.120s	1.121ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.120s	1.121ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.120s	1.121ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.120s	1.121ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.160s	49.672us	1	1	100.00
		edn_sec_cm	5.120s	1.121ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.160s	49.672us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.200s	126.722us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	50.010s	10.714ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00