HMAC Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.240s 123.475us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.700s 17.255us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.760s 26.078us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.660s 647.633us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.700s 108.836us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 10.582m 334.247ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.760s 26.078us 1 1 100.00
hmac_csr_aliasing 4.700s 108.836us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.826m 2.762ms 1 1 100.00
V2 back_pressure hmac_back_pressure 14.930s 666.513us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.228m 13.531ms 1 1 100.00
hmac_test_sha384_vectors 7.710m 16.133ms 1 1 100.00
hmac_test_sha512_vectors 18.850s 237.877us 1 1 100.00
hmac_test_hmac256_vectors 6.520s 190.493us 1 1 100.00
hmac_test_hmac384_vectors 11.330s 327.748us 1 1 100.00
hmac_test_hmac512_vectors 8.770s 240.294us 1 1 100.00
V2 burst_wr hmac_burst_wr 1.670s 20.786us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 9.589m 5.247ms 1 1 100.00
V2 error hmac_error 58.520s 6.378ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 25.040s 3.612ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.240s 123.475us 1 1 100.00
hmac_long_msg 1.826m 2.762ms 1 1 100.00
hmac_back_pressure 14.930s 666.513us 1 1 100.00
hmac_datapath_stress 9.589m 5.247ms 1 1 100.00
hmac_burst_wr 1.670s 20.786us 1 1 100.00
hmac_stress_all 28.465m 192.267ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.240s 123.475us 1 1 100.00
hmac_long_msg 1.826m 2.762ms 1 1 100.00
hmac_back_pressure 14.930s 666.513us 1 1 100.00
hmac_datapath_stress 9.589m 5.247ms 1 1 100.00
hmac_wipe_secret 25.040s 3.612ms 1 1 100.00
hmac_test_sha256_vectors 3.228m 13.531ms 1 1 100.00
hmac_test_sha384_vectors 7.710m 16.133ms 1 1 100.00
hmac_test_sha512_vectors 18.850s 237.877us 1 1 100.00
hmac_test_hmac256_vectors 6.520s 190.493us 1 1 100.00
hmac_test_hmac384_vectors 11.330s 327.748us 1 1 100.00
hmac_test_hmac512_vectors 8.770s 240.294us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.240s 123.475us 1 1 100.00
hmac_long_msg 1.826m 2.762ms 1 1 100.00
hmac_back_pressure 14.930s 666.513us 1 1 100.00
hmac_datapath_stress 9.589m 5.247ms 1 1 100.00
hmac_burst_wr 1.670s 20.786us 1 1 100.00
hmac_error 58.520s 6.378ms 1 1 100.00
hmac_wipe_secret 25.040s 3.612ms 1 1 100.00
hmac_test_sha256_vectors 3.228m 13.531ms 1 1 100.00
hmac_test_sha384_vectors 7.710m 16.133ms 1 1 100.00
hmac_test_sha512_vectors 18.850s 237.877us 1 1 100.00
hmac_test_hmac256_vectors 6.520s 190.493us 1 1 100.00
hmac_test_hmac384_vectors 11.330s 327.748us 1 1 100.00
hmac_test_hmac512_vectors 8.770s 240.294us 1 1 100.00
hmac_stress_all 28.465m 192.267ms 1 1 100.00
V2 stress_all hmac_stress_all 28.465m 192.267ms 1 1 100.00
V2 alert_test hmac_alert_test 1.420s 11.449us 1 1 100.00
V2 intr_test hmac_intr_test 1.680s 36.573us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.520s 256.900us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.520s 256.900us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.700s 17.255us 1 1 100.00
hmac_csr_rw 1.760s 26.078us 1 1 100.00
hmac_csr_aliasing 4.700s 108.836us 1 1 100.00
hmac_same_csr_outstanding 2.740s 180.834us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.700s 17.255us 1 1 100.00
hmac_csr_rw 1.760s 26.078us 1 1 100.00
hmac_csr_aliasing 4.700s 108.836us 1 1 100.00
hmac_same_csr_outstanding 2.740s 180.834us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.610s 82.674us 1 1 100.00
hmac_tl_intg_err 2.260s 143.157us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.260s 143.157us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.240s 123.475us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.940s 147.593us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 11.200s 2.146ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.540s 209.598us 1 1 100.00
TOTAL 28 28 100.00