I2C Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	15.160s	5.621ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.780s	730.202us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.620s	64.517us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.530s	172.488us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.120s	221.868us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.330s	181.969us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.100s	36.760us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.530s	172.488us	1	1	100.00
		i2c_csr_aliasing	2.330s	181.969us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	9.970s	310.085us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	6.835m	33.723ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	32.230s	3.290ms	1	1	100.00
V2	host_override	i2c_host_override	1.490s	28.764us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.022m	15.516ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.912m	2.481ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.920s	157.839us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.660s	237.362us	1	1	100.00
		i2c_host_fifo_reset_rx	3.750s	847.312us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.036m	10.698ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	17.240s	978.462us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.590s	466.681us	1	1	100.00
V2	target_glitch	i2c_target_glitch	9.830s	4.768ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	21.090s	20.969ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.530s	759.611us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	36.840s	5.484ms	1	1	100.00
		i2c_target_intr_smoke	5.560s	1.424ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.540s	219.972us	1	1	100.00
		i2c_target_fifo_reset_tx	1.790s	326.410us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.923m	54.590ms	1	1	100.00
		i2c_target_stress_rd	36.840s	5.484ms	1	1	100.00
		i2c_target_intr_stress_wr	8.250s	4.079ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.870s	3.794ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.880s	353.327us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.020s	14.042ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.800s	732.291us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.320s	922.081us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.280s	151.457us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	32.230s	3.290ms	1	1	100.00
		i2c_host_perf_precise	3.699m	24.454ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	17.240s	978.462us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.170s	437.153us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.900s	1.791ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.670s	1.129ms	1	1	100.00
		i2c_target_nack_txstretch	2.380s	271.081us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	10.980s	713.923us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.560s	473.915us	1	1	100.00
V2	alert_test	i2c_alert_test	1.570s	44.515us	1	1	100.00
V2	intr_test	i2c_intr_test	1.610s	42.658us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.980s	44.070us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.980s	44.070us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.620s	64.517us	1	1	100.00
		i2c_csr_rw	1.530s	172.488us	1	1	100.00
		i2c_csr_aliasing	2.330s	181.969us	1	1	100.00
		i2c_same_csr_outstanding	1.990s	349.045us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.620s	64.517us	1	1	100.00
		i2c_csr_rw	1.530s	172.488us	1	1	100.00
		i2c_csr_aliasing	2.330s	181.969us	1	1	100.00
		i2c_same_csr_outstanding	1.990s	349.045us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.230s	1.545ms	1	1	100.00
		i2c_sec_cm	1.850s	70.168us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.230s	1.545ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.630s	749.908us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.240s	59.075us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.380s	4.233ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.62612955411832955924412187519077723342462756109847804040540363099193450243338
      Line 126, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 33722919625 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @10270728
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.67008233010364136092844222648879801571951546779359319844214220490087699808018
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  59075435 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 106 [0x6a])
        UVM_INFO @  59075435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.26192226363849703931490613134813100453026331519114572636014651277958589572207
      Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 749907690 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 749907690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.90452833083391240040187156268508902417718946045694562092165967682871205062477
      Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4233321922 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 4233321922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---