KEYMGR Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.330s	76.313us	1	1	100.00
V1	random	keymgr_random	2.690s	102.403us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.750s	23.191us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.050s	209.848us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.110s	962.846us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.790s	379.393us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.870s	35.119us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.050s	209.848us	1	1	100.00
		keymgr_csr_aliasing	6.790s	379.393us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.800s	123.391us	1	1	100.00
V2	sideload	keymgr_sideload	2.620s	34.806us	1	1	100.00
		keymgr_sideload_kmac	4.430s	163.015us	1	1	100.00
		keymgr_sideload_aes	26.780s	1.263ms	1	1	100.00
		keymgr_sideload_otbn	26.760s	8.962ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.210s	148.475us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.700s	481.185us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.450s	324.530us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	10.550s	339.424us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	7.260s	464.220us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.430s	72.450us	1	1	100.00
V2	stress_all	keymgr_stress_all	24.670s	3.562ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.630s	27.592us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.590s	40.611us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.920s	39.603us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.920s	39.603us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.750s	23.191us	1	1	100.00
		keymgr_csr_rw	2.050s	209.848us	1	1	100.00
		keymgr_csr_aliasing	6.790s	379.393us	1	1	100.00
		keymgr_same_csr_outstanding	2.300s	45.711us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.750s	23.191us	1	1	100.00
		keymgr_csr_rw	2.050s	209.848us	1	1	100.00
		keymgr_csr_aliasing	6.790s	379.393us	1	1	100.00
		keymgr_same_csr_outstanding	2.300s	45.711us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
		keymgr_tl_intg_err	3.050s	236.941us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.940s	792.907us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.940s	792.907us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.940s	792.907us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.940s	792.907us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	8.040s	704.777us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.050s	236.941us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.940s	792.907us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.800s	123.391us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.690s	102.403us	1	1	100.00
		keymgr_csr_rw	2.050s	209.848us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.690s	102.403us	1	1	100.00
		keymgr_csr_rw	2.050s	209.848us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.690s	102.403us	1	1	100.00
		keymgr_csr_rw	2.050s	209.848us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.700s	481.185us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	7.260s	464.220us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	7.260s	464.220us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.690s	102.403us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.930s	58.262us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.480s	83.441us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.700s	481.185us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.480s	83.441us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.480s	83.441us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.480s	83.441us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.620s	536.795us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.480s	83.441us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.510s	191.398us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.64760557923382494538387316693362375307783552145807402440307168614628255317205
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @  45710613 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @  45710613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---