KMAC/UNMASKED Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	20.600s	6.375ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.680s	27.226us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.760s	16.360us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.210s	2.304ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.410s	1.936ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.320s	95.165us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.760s	16.360us	1	1	100.00
		kmac_csr_aliasing	7.410s	1.936ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.600s	21.545us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.940s	70.016us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	29.172m	84.848ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.660m	10.307ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.057m	95.337ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.994m	76.626ms	1	1	100.00
		kmac_test_vectors_sha3_384	13.463m	52.221ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.650s	969.301us	1	1	100.00
		kmac_test_vectors_shake_128	1.645m	2.155ms	1	1	100.00
		kmac_test_vectors_shake_256	1.649m	7.405ms	1	1	100.00
		kmac_test_vectors_kmac	3.050s	444.717us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.640s	92.001us	1	1	100.00
V2	sideload	kmac_sideload	4.655m	62.165ms	1	1	100.00
V2	app	kmac_app	2.017m	15.605ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.053m	6.157ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.021m	35.397ms	1	1	100.00
V2	error	kmac_error	1.719m	8.530ms	1	1	100.00
V2	key_error	kmac_key_error	6.250s	1.546ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.090s	187.300us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.590s	2.836ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.270s	527.256us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	25.810s	16.740ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.290s	179.048us	1	1	100.00
V2	stress_all	kmac_stress_all	4.162m	15.341ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.560s	10.741us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	51.372us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.000s	212.592us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.000s	212.592us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.680s	27.226us	1	1	100.00
		kmac_csr_rw	1.760s	16.360us	1	1	100.00
		kmac_csr_aliasing	7.410s	1.936ms	1	1	100.00
		kmac_same_csr_outstanding	2.120s	69.020us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.680s	27.226us	1	1	100.00
		kmac_csr_rw	1.760s	16.360us	1	1	100.00
		kmac_csr_aliasing	7.410s	1.936ms	1	1	100.00
		kmac_same_csr_outstanding	2.120s	69.020us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.170s	84.595us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.170s	84.595us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.170s	84.595us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.170s	84.595us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.210s	1.387ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	42.850s	4.750ms	1	1	100.00
		kmac_tl_intg_err	1.930s	23.099us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.930s	23.099us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.290s	179.048us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	20.600s	6.375ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.655m	62.165ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.170s	84.595us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	42.850s	4.750ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	42.850s	4.750ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	42.850s	4.750ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	20.600s	6.375ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.290s	179.048us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	42.850s	4.750ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	26.830s	6.510ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	20.600s	6.375ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.200s	3.525ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.77553929192662675668826992706753299907131282385739752081259188123929483827722
      Line 143, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3524960301 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3524960301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.26635183781477914485486634480538991537574892912037446142069894329344962495526
      Line 93, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @  23098839 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @  23098839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---