RV_TIMER Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.650s	43.832us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.010s	38.500us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.620s	13.876us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.260s	761.748us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.750s	19.856us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.610s	32.737us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.620s	13.876us	1	1	100.00
		rv_timer_csr_aliasing	1.750s	19.856us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.670s	109.568us	1	1	100.00
V2	disabled	rv_timer_disabled	2.360s	1.520ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	19.220s	45.171ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	19.220s	45.171ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.210s	4.036ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.530s	18.819us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.520s	15.266us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.240s	90.909us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.240s	90.909us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.010s	38.500us	1	1	100.00
		rv_timer_csr_rw	1.620s	13.876us	1	1	100.00
		rv_timer_csr_aliasing	1.750s	19.856us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	112.108us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.010s	38.500us	1	1	100.00
		rv_timer_csr_rw	1.620s	13.876us	1	1	100.00
		rv_timer_csr_aliasing	1.750s	19.856us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	112.108us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.780s	248.117us	1	1	100.00
		rv_timer_tl_intg_err	1.760s	90.325us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.760s	90.325us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	33.190s	15.233ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.480s	41.846us	1	1	100.00
		rv_timer_max	1.490s	13.384us	1	1	100.00
		TOTAL			19	19	100.00