SPI_DEVICE/1R1W Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.433m	96.179ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.650s	21.268us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.010s	258.852us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.070s	1.813ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	12.120s	3.373ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.320s	267.183us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.010s	258.852us	1	1	100.00
		spi_device_csr_aliasing	12.120s	3.373ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.700s	13.720us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.400s	192.542us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.820s	21.639us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.710s	1.065us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.700s	2.193us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.500s	21.872us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.500s	21.872us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.430s	321.894us	1	1	100.00
		spi_device_tpm_sts_read	1.650s	56.422us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	12.970s	2.807ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.980s	7.167ms	1	1	100.00
		spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.740s	13.696ms	1	1	100.00
		spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.740s	13.696ms	1	1	100.00
		spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.330s	1.629ms	1	1	100.00
		spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.330s	1.629ms	1	1	100.00
		spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.330s	1.629ms	1	1	100.00
		spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.330s	1.629ms	1	1	100.00
		spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.330s	1.629ms	1	1	100.00
		spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	9.080s	5.395ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.660s	268.330us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.660s	268.330us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.660s	268.330us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.160s	107.909us	1	1	100.00
		spi_device_read_buffer_direct	15.490s	6.225ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.660s	268.330us	1	1	100.00
		spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	34.460s	3.251ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.810s	292.680us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.810s	292.680us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.433m	96.179ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	19.460s	14.500ms	1	1	100.00
V2	stress_all	spi_device_stress_all	58.320s	14.442ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.560s	29.312us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.660s	30.411us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.690s	1.434ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.690s	1.434ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.650s	21.268us	1	1	100.00
		spi_device_csr_rw	3.010s	258.852us	1	1	100.00
		spi_device_csr_aliasing	12.120s	3.373ms	1	1	100.00
		spi_device_same_csr_outstanding	4.120s	168.690us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.650s	21.268us	1	1	100.00
		spi_device_csr_rw	3.010s	258.852us	1	1	100.00
		spi_device_csr_aliasing	12.120s	3.373ms	1	1	100.00
		spi_device_same_csr_outstanding	4.120s	168.690us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.970s	71.431us	1	1	100.00
		spi_device_tl_intg_err	16.960s	2.192ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.960s	2.192ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	26.540s	11.247ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.67617387028756897767667459976053112342703884233423631725650510387649413231176
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    865113 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[89])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    865113 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    865113 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[985])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.113711743845208709511461396671158300009144529782414362349945595818880106741927
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1488566 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1488566 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1548566 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x636bc4 [11000110110101111000100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1548566 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x636bc4 [11000110110101111000100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])