SRAM_CTRL/MAIN Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	21.050s	826.458us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.710s	45.256us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.620s	50.172us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.270s	152.270us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.690s	43.525us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.140s	718.929us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.620s	50.172us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	43.525us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.064m	41.414ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.907m	48.582ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.592m	14.283ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.151m	5.521ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	18.783m	144.207ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	11.805m	66.822ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	22.270s	7.452ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.711m	28.324ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	3.520s	759.970us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.705m	6.462ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	25.740s	1.205ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.950s	685.890us	1	1	100.00
		sram_ctrl_throughput_w_readback	13.800s	779.348us	1	1	100.00
V2	regwen	sram_ctrl_regwen	11.040m	33.972ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.400s	1.248ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	15.829m	56.534ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.560s	14.209us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.420s	287.630us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.420s	287.630us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.710s	45.256us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	50.172us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	43.525us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	13.179us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.710s	45.256us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	50.172us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	43.525us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	13.179us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.120s	11.559ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.750s	9.873us	0	1	0.00
		sram_ctrl_tl_intg_err	2.640s	147.026us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.750s	9.873us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.640s	147.026us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.040m	33.972ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	11.040m	33.972ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.620s	50.172us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.711m	28.324ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.711m	28.324ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.711m	28.324ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	22.270s	7.452ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.940s	2.653ms	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.120s	11.559ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.060s	1.002ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	21.050s	826.458us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	21.050s	826.458us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.711m	28.324ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.750s	9.873us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	22.270s	7.452ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.750s	9.873us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.750s	9.873us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	21.050s	826.458us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.750s	9.873us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	43.120s	5.701ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.110234608443887665213591707982508288681300208903460674811450220754241799512619
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2653271983 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2653271983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.39044502252270636129121834320416699704608284936244705198732221735747940293399
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9872566 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9872566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---