SRAM_CTRL/RET Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.046m	4.248ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.630s	41.189us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.730s	15.979us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.050s	68.335us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.560s	22.372us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.870s	65.637us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.730s	15.979us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	22.372us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.290s	911.696us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.500s	339.277us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.731m	13.780ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.715m	2.374ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	56.150s	22.032ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	14.470m	22.216ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.620s	780.466us	1	1	100.00
V2	executable	sram_ctrl_executable	1.052m	3.825ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	42.820s	2.244ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.203m	33.352ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	12.770s	858.340us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	16.470s	135.314us	1	1	100.00
		sram_ctrl_throughput_w_readback	35.160s	2.176ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	11.019m	44.561ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.510s	137.730us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	25.961m	9.566ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.510s	29.444us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.180s	124.318us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.180s	124.318us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.630s	41.189us	1	1	100.00
		sram_ctrl_csr_rw	1.730s	15.979us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	22.372us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	48.510us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.630s	41.189us	1	1	100.00
		sram_ctrl_csr_rw	1.730s	15.979us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	22.372us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	48.510us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.330s	378.261us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.850s	3.611us	0	1	0.00
		sram_ctrl_tl_intg_err	3.280s	471.057us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.850s	3.611us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.280s	471.057us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.019m	44.561ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	11.019m	44.561ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.730s	15.979us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.052m	3.825ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.052m	3.825ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.052m	3.825ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.620s	780.466us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.830s	51.664us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.330s	378.261us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.890s	227.180us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.046m	4.248ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.046m	4.248ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.052m	3.825ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.850s	3.611us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.620s	780.466us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.850s	3.611us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.850s	3.611us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.046m	4.248ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.850s	3.611us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.197m	2.179ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.24127993770603426842197024986076794934904125954060144645227149238109449019290
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3610698 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3610698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---