UART Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	9.110s	5.540ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.540s	14.223us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.550s	16.913us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.930s	60.263us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.600s	42.444us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.540s	13.771us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.550s	16.913us	1	1	100.00
		uart_csr_aliasing	1.600s	42.444us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	50.570s	74.931ms	1	1	100.00
V2	parity	uart_smoke	9.110s	5.540ms	1	1	100.00
		uart_tx_rx	50.570s	74.931ms	1	1	100.00
V2	parity_error	uart_intr	22.330s	78.760ms	1	1	100.00
		uart_rx_parity_err	11.280s	11.054ms	1	1	100.00
V2	watermark	uart_tx_rx	50.570s	74.931ms	1	1	100.00
		uart_intr	22.330s	78.760ms	1	1	100.00
V2	fifo_full	uart_fifo_full	45.890s	42.159ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.314m	204.289ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.724m	96.442ms	1	1	100.00
V2	rx_frame_err	uart_intr	22.330s	78.760ms	1	1	100.00
V2	rx_break_err	uart_intr	22.330s	78.760ms	1	1	100.00
V2	rx_timeout	uart_intr	22.330s	78.760ms	1	1	100.00
V2	perf	uart_perf	4.882m	20.591ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.240s	4.480ms	1	1	100.00
V2	line_loopback	uart_loopback	3.240s	4.480ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	13.350s	11.714ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	12.750s	34.928ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.240s	9.675ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	5.180s	1.490ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.460m	81.573ms	1	1	100.00
V2	stress_all	uart_stress_all	1.980m	79.105ms	1	1	100.00
V2	alert_test	uart_alert_test	1.570s	24.878us	1	1	100.00
V2	intr_test	uart_intr_test	1.560s	12.289us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.190s	33.661us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.190s	33.661us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.540s	14.223us	1	1	100.00
		uart_csr_rw	1.550s	16.913us	1	1	100.00
		uart_csr_aliasing	1.600s	42.444us	1	1	100.00
		uart_same_csr_outstanding	1.630s	34.266us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.540s	14.223us	1	1	100.00
		uart_csr_rw	1.550s	16.913us	1	1	100.00
		uart_csr_aliasing	1.600s	42.444us	1	1	100.00
		uart_same_csr_outstanding	1.630s	34.266us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.700s	70.311us	1	1	100.00
		uart_tl_intg_err	1.830s	239.205us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.830s	239.205us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	19.850s	11.476ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00