CHIP Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: `b6a2634`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.534m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.534m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	41.782s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	35.686s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	33.752s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.983m	5.360ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.983m	5.360ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.983m	5.360ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	41.200s	10.160us	0	1	0.00
		chip_sw_example_manufacturer	2.637m		0	1	0.00
		chip_sw_example_concurrency	4.526m	3.676ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.585s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.780s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.180s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.180s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.380s	57.936us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.536m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.844m	9.513ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.369m	5.836ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.696s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	13.638s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	11.775s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.746s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.530s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.530s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.943m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.639m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.970m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.970m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.015m	5.192ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.049m	4.019ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.735m	13.327ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.660s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.333s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.760m	14.188ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.585m	5.824ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.118m	18.023ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.118m	18.023ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.803s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.624m	5.064ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.624m	5.064ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.510m	18.018ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.722m	3.516ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.210m	3.889ms	1	1	100.00
		chip_sw_aes_idle	3.802m	4.806ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.221m	5.957ms	1	1	100.00
		chip_sw_kmac_idle	3.949m	3.503ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.324s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.508s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.384s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.938s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	16.583s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.152s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.857s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.924s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.335s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.373s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.716s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	16.583s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.152s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.857s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.924s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.335s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.373s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.716s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.359s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.240s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	56.750s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	50.220s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	48.500s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.552s		0	1	0.00
		chip_sw_clkmgr_jitter	3.916m	3.678ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.481m	5.006ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.810s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	48.380s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	50.430s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	52.280s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	47.880s	10.320us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	58.400s	10.200us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	15.496s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.724s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.534s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.049s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	17.987m	16.251ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.406m	11.430ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.624m	5.064ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	17.417s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.406m	11.430ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	13.207s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	17.625s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	27.563s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	23.348s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.556s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	17.987m	16.251ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.735m	13.327ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	17.992m	20.023ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.504m	7.780ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.118m	7.046ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.364m	3.095ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	17.987m	16.251ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.121s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.788s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	17.987m	16.251ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.678s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.118m	7.046ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.862s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.839s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.890s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.776s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.701s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.836s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.788s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	19.190s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	23.618s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.190s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.190s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.190s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.348m	10.184ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.692s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	24.933s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	19.277s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	25.591s		0	1	0.00
		chip_sw_lc_ctrl_transition	19.190s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.968m	8.537ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.324m	12.923ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.497s		0	1	0.00
		chip_prim_tl_access	8.849m	13.425ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	16.583s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.152s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.857s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.924s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.335s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.373s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.716s		0	1	0.00
		chip_rv_dm_lc_disabled	10.760m	14.188ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.447m	4.399ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	46.240s	10.220us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.928m	4.605ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.802m	4.806ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.829m	4.156ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	56.750s	10.140us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.221m	5.957ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.432m	3.223ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.129m	5.488ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	48.500s	10.220us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.968m	8.537ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.190s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	40.380s	10.360us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.235m	5.806ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.949m	3.503ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.483s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.483s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.705s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.959m	4.846ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.672s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.968m	8.537ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	50.220s	10.220us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	14.979s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.359s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.210m	3.889ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.210m	3.889ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.210m	3.889ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.958m	5.955ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.324m	12.923ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.324m	12.923ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.548m	6.756ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.552s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.497s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	17.987m	16.251ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.970m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.190s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.958m	5.955ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.968m	8.537ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.548m	6.756ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.305m	4.029ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.958m	5.955ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.968m	8.537ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.548m	6.756ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.305m	4.029ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.190s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.416s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	23.618s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.692s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	24.933s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	19.277s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	25.591s		0	1	0.00
		chip_sw_lc_ctrl_transition	19.190s		0	1	0.00
		chip_prim_tl_access	8.849m	13.425ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.849m	13.425ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	38.243s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.264s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.724s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.359s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.240s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	56.750s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	50.220s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	48.500s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.552s		0	1	0.00
		chip_sw_clkmgr_jitter	3.916m	3.678ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.431m	9.717ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.431m	9.717ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.510m	3.771ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.168m	4.400ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.723m	4.781ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.474m	7.036ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.604m	4.468ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.011m	4.961ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.305m	4.029ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	17.992m	20.023ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	17.992m	20.023ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.309m	3.688ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.612m	5.482ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.293m	4.489ms	1	1	100.00
		chip_sw_csrng_smoketest	3.808m	5.411ms	1	1	100.00
		chip_sw_gpio_smoketest	3.611m	3.218ms	1	1	100.00
		chip_sw_hmac_smoketest	4.232m	4.974ms	1	1	100.00
		chip_sw_kmac_smoketest	3.633m	5.033ms	1	1	100.00
		chip_sw_otbn_smoketest	4.146m	4.030ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.031m	4.314ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.615m	4.500ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.702m	4.286ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.306m	3.688ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.167m	4.846ms	1	1	100.00
		chip_sw_uart_smoketest	3.503m	4.591ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.739s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.585s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.536m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.302s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.337m	3.802ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.615m	4.205ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.092m	4.723ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.151m	4.212ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.454s		0	1	0.00
		chip_rv_dm_lc_disabled	10.760m	14.188ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	16.795s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.582s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	21.068s		0	1	0.00
		chip_sw_lc_walkthrough_rma	16.517s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.454s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.376s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	14.381s		0	1	0.00
		rom_volatile_raw_unlock	11.334s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.838s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	48.817s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.493m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.048m	3.592ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.048m	3.592ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.180s		0	1	0.00
		chip_same_csr_outstanding	9.280s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.180s		0	1	0.00
		chip_same_csr_outstanding	9.280s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	29.560s	27.951us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.940s	12.724us	1	1	100.00
		xbar_smoke_large_delays	4.951m	2.477ms	1	1	100.00
		xbar_smoke_slow_rsp	4.727m	1.777ms	1	1	100.00
		xbar_random_zero_delays	1.290m	64.214us	1	1	100.00
		xbar_random_large_delays	6.298m	3.232ms	1	1	100.00
		xbar_random_slow_rsp	11.095m	3.815ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.145m	135.282us	1	1	100.00
		xbar_error_and_unmapped_addr	58.690s	143.259us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.815m	545.827us	1	1	100.00
		xbar_error_and_unmapped_addr	58.690s	143.259us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.909m	80.481us	1	1	100.00
		xbar_access_same_device_slow_rsp	43.482m	17.192ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	12.620s	10.091us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.500m	312.456us	1	1	100.00
		xbar_stress_all_with_error	9.965m	1.795ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.828m	2.082ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.841m	133.519us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.146s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.659s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.940s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.965s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.541s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.415s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.681s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.737s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.430s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.022s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.741s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.615s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.588s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.636s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	13.041s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	13.072s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.368s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.908s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.270s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.088s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.778s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.758s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.929s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.283s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.359s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.791s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.247s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.045s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.782s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.836s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.398s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.438s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.487s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.779s		0	1	0.00
		rom_e2e_asm_init_dev	12.153s		0	1	0.00
		rom_e2e_asm_init_prod	11.806s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.074s		0	1	0.00
		rom_e2e_asm_init_rma	11.703s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.250s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.412s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.039s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.761s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.498m	5.721ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.601m	4.240ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.037s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.812s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.200s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.396s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	17.987m	16.251ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.324s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.962m	12.918ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.515s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.870s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.037s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.812s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.200s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.454s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.352s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.633s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.163m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.318m	13.016ms	1	1	100.00
		chip_plic_all_irqs_0	9.681m	7.205ms	1	1	100.00
		chip_plic_all_irqs_10	9.240m	6.565ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.086m	3.938ms	1	1	100.00
		chip_sw_dma_abort	4.297m	4.608ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.430s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.141s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.899s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.578s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.447s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.065s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.860s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.276s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.563s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.241s		0	1	0.00
		chip_sw_mbx_smoketest	4.480m	5.731ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 140 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.4126071937000673465958645204039233181247391357300126098518754769722272335303
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (130e5f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 145.696s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.2244036421783365593664889609321622417128489296150878681229086248325346945759
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (697874)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 106.780s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.11767560227648446538076398186519058830564899145833411755065777745546553831996
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (d48255)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 106.358s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.59871989877765686148572804245820660859862666853482304868382213151017072852910
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (459adc)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 88.290s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.80841214333649898517136897204076798272342292974420797886016230624560606801370
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b9b0d7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 82.156s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 135 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.76357988326233099374438089512795756772924939678590864222954968558554073593584
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.69755000899138542866980637738256138580450737219423954809552448880724158858110
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.14215066005735056754764362372650670052631631689667041817984227376142397692063
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.84334634482433215366132802130245184022378646967022977609820550437707124729185
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.60499223400295734868921546339093296605838144642867609796844069735473000169
    Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.11716091374928315644668354657077534378369764995125394709082505043598134101756
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.84325588753858979866789176048844331105848278155950531934427264722408081028786
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.12129235568900332995184555065834132092941430011435645233762920556439272110614
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.82375349344172724054386291821250070071598251829160692816175325817665216248589
Line 492, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20022.500132 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20022.500132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.48710588214444895709335826560264577278108362766922786183905558865001933337374
Line 451, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18023.093479 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18023.093479 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.106316841305545819312526253420856216000349429256250114932020278452646761878435
Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.475857 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.475857 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.4133168431067195099148575399701279990210170312539588194948925510807332023164
Line 461, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8537.373066 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (57192805189719790494882651345395981366003204813205949688179555664934229006848 [0x7e71fb07d906e0f31b217589e938a1ba4a5ff41807f37723a212787580c85a00] vs 76612889071033589849757312339272816669960310227980107415687049106489935282072 [0xa9615bc9a46144309daeecf50232a815f04f984c0794367737e283c6ee7e3f98])
  UVM_INFO @ 8537.373066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.27989488311107438908497843871096220566973854340190708759115830867625236788776
Line 461, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 10183.985704 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (102251601334104422631136514895059039713876618868833904027994855037767414725312 [0xe2105afddc695c2af43baa1787b6f7cf11b4f672f7f9e45dd0d7a0b499743ac0] vs 26438822948630327453038808053584179144948588120759935395185534762394950582030 [0x3a73d7eefade3cb59f685d0dbc243b2bb7b3e7e1a236e1b7fcfc6c33f5683f0e])
  UVM_INFO @ 10183.985704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.114058234805742056491033580768513025706955853943745323789537396712625103560641
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5192.142833 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hcd052fdf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h0  a_user: 'h26956  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5192.142833 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.3141864758883468619700009096873503816435662781593707269897123423850759836835
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4018.863148 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h5306c37f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h1  a_user: 'h248c8  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4018.863148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.88302581922539423275002874304583259444231454529066631216491115185717303961437
    Line 620, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.83058152509216043267610059011220121031856379078162418298080362707892433193067
    Line 478, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5836.205026 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5836.205026 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.7164366122927169573945825753532745530055938351472006890390113956721650201364
    Line 707, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 7046.017672 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 7046.017672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.84003789604018364468922931891068359996486045570056591147583487680479710324243
    Line 450, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3770.514456 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3770.514456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.16117209312575208915144952876664967026490099614051694899514973970166899311927
    Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4399.932720 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4399.932720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.114147947283998997366610719479941947697669205783287101378275543844819301204371
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5063.768676 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5063.768676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.4205043523194964801484954067095715008557425689399265688550293590736338847317
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 7036.444300 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 7036.444300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.94464927155479809696862157623417743931559122159573585415241057963024133411302
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36224) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.515331589398875434748580369201163421412568960955717386582081041707751961477
Line 263, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3592.474736 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36224) { a_addr: 'h406ac  a_data: 'h12e9c65b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h189d2  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3592.474736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.23110288986209679406931966098888735973578337167135602604882348112352966442890
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13326.974188 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13326.974188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.55862862608524117173845542428263745834544774951202675454473877633765098286865
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.50261013089091854643420408114952874824828040325756746023064144484495747347659
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4608.269404 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4608.269404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```