DMA Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	298.304us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	714.259us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	11.000s	343.231us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	114.649us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	32.198us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	3.709ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	275.130us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	31.732us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	32.198us	1	1	100.00
		dma_csr_aliasing	6.000s	275.130us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	45.000s	2.978ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	8.367m	170.418ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	18.417m	435.749ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.617m	16.110ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	8.367m	170.418ms	1	1	100.00
V2	dma_abort	dma_abort	7.000s	1.016ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.150m	11.386ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	40.471us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	153.960us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	153.960us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	114.649us	1	1	100.00
		dma_csr_rw	4.000s	32.198us	1	1	100.00
		dma_csr_aliasing	6.000s	275.130us	1	1	100.00
		dma_same_csr_outstanding	4.000s	63.442us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	114.649us	1	1	100.00
		dma_csr_rw	4.000s	32.198us	1	1	100.00
		dma_csr_aliasing	6.000s	275.130us	1	1	100.00
		dma_same_csr_outstanding	4.000s	63.442us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	18.000s	789.292us	1	1	100.00
		dma_generic_stress	2.617m	16.110ms	1	1	100.00
		dma_handshake_stress	8.367m	170.418ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	105.721us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.850m	42.603ms	1	1	100.00
		dma_longer_transfer	39.000s	3.800ms	1	1	100.00
		TOTAL			21	21	100.00