EDN Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.760s	61.456us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.800s	71.779us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.620s	12.872us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.400s	227.533us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.880s	25.316us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.980s	157.502us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.620s	12.872us	1	1	100.00
		edn_csr_aliasing	1.880s	25.316us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	3.730s	165.098us	1	1	100.00
V2	csrng_commands	edn_genbits	3.730s	165.098us	1	1	100.00
V2	genbits	edn_genbits	3.730s	165.098us	1	1	100.00
V2	interrupts	edn_intr	1.780s	34.898us	1	1	100.00
V2	alerts	edn_alert	1.840s	23.520us	1	1	100.00
V2	errs	edn_err	1.800s	19.119us	1	1	100.00
V2	disable	edn_disable	1.610s	44.160us	1	1	100.00
		edn_disable_auto_req_mode	2.260s	38.279us	1	1	100.00
V2	stress_all	edn_stress_all	1.870s	64.515us	1	1	100.00
V2	intr_test	edn_intr_test	1.890s	37.641us	1	1	100.00
V2	alert_test	edn_alert_test	1.940s	12.723us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.740s	92.515us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.740s	92.515us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.800s	71.779us	1	1	100.00
		edn_csr_rw	1.620s	12.872us	1	1	100.00
		edn_csr_aliasing	1.880s	25.316us	1	1	100.00
		edn_same_csr_outstanding	1.980s	100.848us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.800s	71.779us	1	1	100.00
		edn_csr_rw	1.620s	12.872us	1	1	100.00
		edn_csr_aliasing	1.880s	25.316us	1	1	100.00
		edn_same_csr_outstanding	1.980s	100.848us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.250s	1.756ms	1	1	100.00
		edn_tl_intg_err	2.820s	80.612us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.860s	74.728us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.840s	23.520us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.250s	1.756ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.250s	1.756ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.250s	1.756ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.250s	1.756ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.840s	23.520us	1	1	100.00
		edn_sec_cm	6.250s	1.756ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.840s	23.520us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.820s	80.612us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	27.840s	1.378ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00