HMAC Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.900s 801.500us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.770s 21.112us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.620s 28.209us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.000s 835.629us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.830s 2.317ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.930s 46.461us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.620s 28.209us 1 1 100.00
hmac_csr_aliasing 7.830s 2.317ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 16.200s 1.627ms 1 1 100.00
V2 back_pressure hmac_back_pressure 41.990s 1.420ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.170m 24.283ms 1 1 100.00
hmac_test_sha384_vectors 24.020s 1.249ms 1 1 100.00
hmac_test_sha512_vectors 21.910s 278.819us 1 1 100.00
hmac_test_hmac256_vectors 9.760s 1.124ms 1 1 100.00
hmac_test_hmac384_vectors 10.410s 253.910us 1 1 100.00
hmac_test_hmac512_vectors 12.140s 364.103us 1 1 100.00
V2 burst_wr hmac_burst_wr 4.690s 265.780us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 6.268m 2.445ms 1 1 100.00
V2 error hmac_error 44.470s 4.435ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 51.520s 5.568ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.900s 801.500us 1 1 100.00
hmac_long_msg 16.200s 1.627ms 1 1 100.00
hmac_back_pressure 41.990s 1.420ms 1 1 100.00
hmac_datapath_stress 6.268m 2.445ms 1 1 100.00
hmac_burst_wr 4.690s 265.780us 1 1 100.00
hmac_stress_all 24.329m 156.997ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.900s 801.500us 1 1 100.00
hmac_long_msg 16.200s 1.627ms 1 1 100.00
hmac_back_pressure 41.990s 1.420ms 1 1 100.00
hmac_datapath_stress 6.268m 2.445ms 1 1 100.00
hmac_wipe_secret 51.520s 5.568ms 1 1 100.00
hmac_test_sha256_vectors 3.170m 24.283ms 1 1 100.00
hmac_test_sha384_vectors 24.020s 1.249ms 1 1 100.00
hmac_test_sha512_vectors 21.910s 278.819us 1 1 100.00
hmac_test_hmac256_vectors 9.760s 1.124ms 1 1 100.00
hmac_test_hmac384_vectors 10.410s 253.910us 1 1 100.00
hmac_test_hmac512_vectors 12.140s 364.103us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.900s 801.500us 1 1 100.00
hmac_long_msg 16.200s 1.627ms 1 1 100.00
hmac_back_pressure 41.990s 1.420ms 1 1 100.00
hmac_datapath_stress 6.268m 2.445ms 1 1 100.00
hmac_burst_wr 4.690s 265.780us 1 1 100.00
hmac_error 44.470s 4.435ms 1 1 100.00
hmac_wipe_secret 51.520s 5.568ms 1 1 100.00
hmac_test_sha256_vectors 3.170m 24.283ms 1 1 100.00
hmac_test_sha384_vectors 24.020s 1.249ms 1 1 100.00
hmac_test_sha512_vectors 21.910s 278.819us 1 1 100.00
hmac_test_hmac256_vectors 9.760s 1.124ms 1 1 100.00
hmac_test_hmac384_vectors 10.410s 253.910us 1 1 100.00
hmac_test_hmac512_vectors 12.140s 364.103us 1 1 100.00
hmac_stress_all 24.329m 156.997ms 1 1 100.00
V2 stress_all hmac_stress_all 24.329m 156.997ms 1 1 100.00
V2 alert_test hmac_alert_test 1.470s 32.961us 1 1 100.00
V2 intr_test hmac_intr_test 1.490s 113.344us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.170s 119.855us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.170s 119.855us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.770s 21.112us 1 1 100.00
hmac_csr_rw 1.620s 28.209us 1 1 100.00
hmac_csr_aliasing 7.830s 2.317ms 1 1 100.00
hmac_same_csr_outstanding 3.260s 124.537us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.770s 21.112us 1 1 100.00
hmac_csr_rw 1.620s 28.209us 1 1 100.00
hmac_csr_aliasing 7.830s 2.317ms 1 1 100.00
hmac_same_csr_outstanding 3.260s 124.537us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.980s 49.863us 1 1 100.00
hmac_tl_intg_err 3.970s 516.925us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.970s 516.925us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.900s 801.500us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.710s 31.138us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 14.690s 1.244ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.060s 60.501us 1 1 100.00
TOTAL 28 28 100.00