I2C Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	38.440s	2.475ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.830s	1.456ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.740s	76.868us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.680s	69.493us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.290s	1.441ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.990s	65.592us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.730s	85.398us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.680s	69.493us	1	1	100.00
		i2c_csr_aliasing	1.990s	65.592us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.260s	197.940us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	10.414m	51.586ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	7.224m	48.470ms	1	1	100.00
V2	host_override	i2c_host_override	1.770s	44.191us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	44.590s	3.252ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.383m	7.923ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.860s	205.643us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.390s	6.215ms	1	1	100.00
		i2c_host_fifo_reset_rx	2.680s	107.323us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	35.550s	10.415ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	19.830s	3.316ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.770s	209.267us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.180s	2.164ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	26.400s	6.467ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.350s	2.218ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	20.620s	28.705ms	1	1	100.00
		i2c_target_intr_smoke	5.810s	12.302ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.660s	439.518us	1	1	100.00
		i2c_target_fifo_reset_tx	1.820s	202.404us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	27.620s	25.274ms	1	1	100.00
		i2c_target_stress_rd	20.620s	28.705ms	1	1	100.00
		i2c_target_intr_stress_wr	1.496m	15.682ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.710s	5.566ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.360s	3.271ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.210s	1.061ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	22.390s	10.135ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.700s	951.948us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.760s	85.109us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	7.224m	48.470ms	1	1	100.00
		i2c_host_perf_precise	1.477m	24.358ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	19.830s	3.316ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.530s	167.375us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.750s	815.006us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.600s	4.287ms	1	1	100.00
		i2c_target_nack_txstretch	2.180s	724.927us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.980s	1.607ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.130s	1.921ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.650s	44.742us	1	1	100.00
V2	intr_test	i2c_intr_test	1.700s	57.644us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.390s	182.022us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.390s	182.022us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.740s	76.868us	1	1	100.00
		i2c_csr_rw	1.680s	69.493us	1	1	100.00
		i2c_csr_aliasing	1.990s	65.592us	1	1	100.00
		i2c_same_csr_outstanding	1.830s	108.883us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.740s	76.868us	1	1	100.00
		i2c_csr_rw	1.680s	69.493us	1	1	100.00
		i2c_csr_aliasing	1.990s	65.592us	1	1	100.00
		i2c_same_csr_outstanding	1.830s	108.883us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.760s	538.202us	1	1	100.00
		i2c_sec_cm	1.890s	148.593us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.760s	538.202us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.260s	210.071us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.720s	102.964us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	23.620s	6.695ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.66936403570833184089452253331839823953777149347888069537313243241422133753408
      Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 210071289 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 210071289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.5835349832730036336198360687400939479948520704908335609680075343701580752447
      Line 101, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6695219365 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6695219365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.52474280950074331857367742288419285740499040541285529759254607236596290535728
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 102964439 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 193 [0xc1])
        UVM_INFO @ 102964439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.36853332604768468179548741743436992320219189595386999306818933879632716658873
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10134779046 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10134779046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---