KEYMGR Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.480s	26.763us	1	1	100.00
V1	random	keymgr_random	4.190s	331.758us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.190s	19.222us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.220s	86.333us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	8.740s	521.963us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	2.570s	384.197us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.280s	284.520us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.220s	86.333us	1	1	100.00
		keymgr_csr_aliasing	2.570s	384.197us	0	1	0.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	4.000s	58.851us	1	1	100.00
V2	sideload	keymgr_sideload	3.200s	34.121us	1	1	100.00
		keymgr_sideload_kmac	3.130s	196.156us	1	1	100.00
		keymgr_sideload_aes	2.700s	240.254us	1	1	100.00
		keymgr_sideload_otbn	2.430s	36.410us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.820s	295.767us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	5.570s	2.109ms	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.140s	393.030us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.710s	719.826us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.900s	73.821us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.000s	278.019us	1	1	100.00
V2	stress_all	keymgr_stress_all	17.240s	502.716us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.840s	18.483us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.700s	68.949us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.830s	125.132us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.830s	125.132us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.190s	19.222us	1	1	100.00
		keymgr_csr_rw	2.220s	86.333us	1	1	100.00
		keymgr_csr_aliasing	2.570s	384.197us	0	1	0.00
		keymgr_same_csr_outstanding	2.620s	40.631us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.190s	19.222us	1	1	100.00
		keymgr_csr_rw	2.220s	86.333us	1	1	100.00
		keymgr_csr_aliasing	2.570s	384.197us	0	1	0.00
		keymgr_same_csr_outstanding	2.620s	40.631us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
		keymgr_tl_intg_err	1.960s	27.903us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.180s	192.573us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.180s	192.573us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.180s	192.573us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.180s	192.573us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.540s	12.733us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.960s	27.903us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.180s	192.573us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.000s	58.851us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.190s	331.758us	1	1	100.00
		keymgr_csr_rw	2.220s	86.333us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.190s	331.758us	1	1	100.00
		keymgr_csr_rw	2.220s	86.333us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.190s	331.758us	1	1	100.00
		keymgr_csr_rw	2.220s	86.333us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.570s	2.109ms	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.900s	73.821us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.900s	73.821us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.190s	331.758us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.690s	51.533us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.750s	371.283us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.570s	2.109ms	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.750s	371.283us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.750s	371.283us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.750s	371.283us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.950s	353.686us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.750s	371.283us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.960s	812.212us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.12886008192612395473444011241619508422536593429019676331013444600233427242729
      Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
        UVM_ERROR @  12732914 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
        UVM_INFO @  12732914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.2781377355678262086147598199766015863946781449442373382807311161221045967792
      Line 93, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @  27903460 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @  27903460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.14096739651836478227711919731621447414431522475629349196041535612532987388077
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
        UVM_ERROR @ 384197196 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
        UVM_INFO @ 384197196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.110887830927347382595692176035395760576591461776305882584378597624860875302709
      Line 1126, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 812212305 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 812212305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---