KMAC/MASKED Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	6.770s	2.375ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.620s	301.056us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.920s	383.697us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.400s	299.795us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.180s	2.897ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.860s	274.874us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.920s	383.697us	1	1	100.00
		kmac_csr_aliasing	7.180s	2.897ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.630s	13.372us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.980s	113.515us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	27.517m	54.460ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.633m	31.268ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.030s	2.848ms	1	1	100.00
		kmac_test_vectors_sha3_256	33.687m	962.382ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.680s	1.735ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.810s	1.079ms	1	1	100.00
		kmac_test_vectors_shake_128	2.576m	8.765ms	1	1	100.00
		kmac_test_vectors_shake_256	31.363m	143.103ms	1	1	100.00
		kmac_test_vectors_kmac	3.740s	604.011us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.640s	124.970us	1	1	100.00
V2	sideload	kmac_sideload	46.790s	2.614ms	1	1	100.00
V2	app	kmac_app	27.370s	1.181ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.099m	31.686ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.677m	2.955ms	1	1	100.00
V2	error	kmac_error	6.610m	24.214ms	1	1	100.00
V2	key_error	kmac_key_error	10.690s	1.422ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	6.390s	199.260us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	20.550s	4.684ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	25.030s	1.229ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	11.910s	4.280ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.450s	90.097us	1	1	100.00
V2	stress_all	kmac_stress_all	11.667m	99.188ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.820s	13.075us	1	1	100.00
V2	alert_test	kmac_alert_test	1.890s	18.734us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.200s	37.700us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.200s	37.700us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.620s	301.056us	1	1	100.00
		kmac_csr_rw	1.920s	383.697us	1	1	100.00
		kmac_csr_aliasing	7.180s	2.897ms	1	1	100.00
		kmac_same_csr_outstanding	2.270s	33.480us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.620s	301.056us	1	1	100.00
		kmac_csr_rw	1.920s	383.697us	1	1	100.00
		kmac_csr_aliasing	7.180s	2.897ms	1	1	100.00
		kmac_same_csr_outstanding	2.270s	33.480us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.660s	245.815us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.660s	245.815us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.660s	245.815us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.660s	245.815us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.940s	391.051us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.115m	13.707ms	1	1	100.00
		kmac_tl_intg_err	1.730s	39.718us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.730s	39.718us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.450s	90.097us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	6.770s	2.375ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	46.790s	2.614ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.660s	245.815us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.115m	13.707ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.115m	13.707ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.115m	13.707ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	6.770s	2.375ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.450s	90.097us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.115m	13.707ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	35.840s	3.670ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	6.770s	2.375ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	7.420s	2.942ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.21657843686591976799666704491791774444177504737087994924443023627801713267211
      Line 83, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2941676230 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2941676230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.5658106319833231232566511864915575181300618748932055619036461277429153209803
      Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
        UVM_ERROR @  39717968 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
        UVM_INFO @  39717968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---