KMAC/UNMASKED Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	31.380s	12.491ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.800s	69.675us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.670s	27.490us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.770s	11.318ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.790s	76.909us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.210s	42.228us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.670s	27.490us	1	1	100.00
		kmac_csr_aliasing	3.790s	76.909us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.510s	13.714us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.160s	31.913us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	5.489m	19.546ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.056m	16.787ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.836m	253.838ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.460s	3.925ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.360s	1.692ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.690s	2.863ms	1	1	100.00
		kmac_test_vectors_shake_128	2.033m	44.478ms	1	1	100.00
		kmac_test_vectors_shake_256	4.190m	392.155ms	1	1	100.00
		kmac_test_vectors_kmac	2.580s	123.019us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.480s	259.484us	1	1	100.00
V2	sideload	kmac_sideload	1.524m	19.041ms	1	1	100.00
V2	app	kmac_app	52.970s	7.012ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.243m	37.736ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.563m	12.094ms	1	1	100.00
V2	error	kmac_error	2.315m	9.176ms	1	1	100.00
V2	key_error	kmac_key_error	3.380s	447.642us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.068m	10.040ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	8.690s	2.275ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	15.410s	1.268ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	5.490s	679.593us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	14.930s	1.068ms	1	1	100.00
V2	stress_all	kmac_stress_all	7.065m	74.754ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.620s	38.785us	1	1	100.00
V2	alert_test	kmac_alert_test	1.690s	24.593us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.120s	188.108us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.120s	188.108us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.800s	69.675us	1	1	100.00
		kmac_csr_rw	1.670s	27.490us	1	1	100.00
		kmac_csr_aliasing	3.790s	76.909us	1	1	100.00
		kmac_same_csr_outstanding	2.420s	38.395us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.800s	69.675us	1	1	100.00
		kmac_csr_rw	1.670s	27.490us	1	1	100.00
		kmac_csr_aliasing	3.790s	76.909us	1	1	100.00
		kmac_same_csr_outstanding	2.420s	38.395us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.220s	85.083us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.220s	85.083us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.220s	85.083us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.220s	85.083us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.670s	248.195us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	22.070s	9.879ms	1	1	100.00
		kmac_tl_intg_err	1.880s	9.667us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.880s	9.667us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	14.930s	1.068ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	31.380s	12.491ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.524m	19.041ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.220s	85.083us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	22.070s	9.879ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	22.070s	9.879ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	22.070s	9.879ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	31.380s	12.491ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	14.930s	1.068ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	22.070s	9.879ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.980s	1.277ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	31.380s	12.491ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.790s	13.344us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			36	40	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.110391565256967315992856107770451790011816139882822490402957229581891833445076
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @ 248194544 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @ 248194544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.75136113638466301596338611073532032788914596111318346000870029197590935263792
      Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @   9666511 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @   9666511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.108210104336277328398998669492676205442349138448073732333369489552130212248052
      Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10039836261 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x920ab000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
        UVM_INFO @ 10039836261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.52700941269622519666946032969640214406848406020112313581327160648376242087021
      Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  13344397 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @  13344397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---