3add6b6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 55.000s | 2.939ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 37.168us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 17.996us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 78.179us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 20.127us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.013us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 17.996us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 20.127us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 59.000s | 17.384ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 28.000s | 1.724ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 57.000s | 1.455ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 14.407us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 976.353ns | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 976.353ns | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 37.168us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 17.996us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 20.127us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 23.362us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 37.168us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 17.996us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 20.127us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 23.362us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 6.000s | 11.821us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 4.556us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_errors has 1 failures.
0.mbx_tl_errors.89041477188984199930602351066711112280083875544044142671524994324808018651342
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 976353 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x165ce405 a_data = 0xb256a23b a_mask = 0x6 a_size = 0x1 a_param = 0x0 a_source = 0xc6 a_opcode = PutFullData a_user = 0x278e8 d_data = 0x768e2a3b d_size = 0x0 d_param = 0x0 d_source = 0x52 d_opcode = AccessAckData d_error = 0 d_user = 1100001111000 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 976353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_csr_mem_rw_with_rand_reset has 1 failures.
0.mbx_csr_mem_rw_with_rand_reset.5158139048618036494373834529233289133551389138037118055835038555808199847369
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1012748 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xb1595c30 a_data = 0x4d51d8da a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xa7 a_opcode = PutFullData a_user = 0x1add4 d_data = 0x4d257fef d_size = 0x0 d_param = 0x0 d_source = 0x97 d_opcode = AccessAckData d_error = 0 d_user = 11101111011011 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1012748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.111211402949776851890211707085324385057771635157387939885063017187107448747801
Line 92, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 4555919 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xb39f7c70 a_data = 0xda4c8e1e a_mask = 0x4 a_size = 0x2 a_param = 0x0 a_source = 0x2c a_opcode = PutPartialData a_user = 0x24548 d_data = 0x31877982 d_size = 0x2 d_param = 0x0 d_source = 0x7b d_opcode = AccessAck d_error = 0 d_user = 1101110010001 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4555919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---