OTBN Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	41.000s	780.980us	1	1	100.00
V1	single_binary	otbn_single	8.000s	51.961us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	29.365us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	41.038us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	75.764us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	38.822us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	34.051us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	41.038us	1	1	100.00
		otbn_csr_aliasing	6.000s	38.822us	1	1	100.00
V1	mem_walk	otbn_mem_walk	21.000s	368.356us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	12.000s	220.959us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	16.000s	160.211us	1	1	100.00
V2	multi_error	otbn_multi_err	38.000s	333.022us	1	1	100.00
V2	back_to_back	otbn_multi	57.000s	231.764us	1	1	100.00
V2	stress_all	otbn_stress_all	1.017m	793.996us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	59.687us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	15.556us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	9.000s	22.692us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	44.318us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	16.615us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	52.179us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	52.179us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	29.365us	1	1	100.00
		otbn_csr_rw	6.000s	41.038us	1	1	100.00
		otbn_csr_aliasing	6.000s	38.822us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	33.772us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	29.365us	1	1	100.00
		otbn_csr_rw	6.000s	41.038us	1	1	100.00
		otbn_csr_aliasing	6.000s	38.822us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	33.772us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	104.612us	1	1	100.00
		otbn_dmem_err	13.000s	19.855us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	55.423us	1	1	100.00
		otbn_controller_ispr_rdata_err	8.000s	78.726us	1	1	100.00
		otbn_mac_bignum_acc_err	21.000s	279.817us	1	1	100.00
		otbn_urnd_err	7.000s	10.099us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	42.633us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	12.429us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	90.212us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	11.000s	38.054us	0	1	0.00
		otbn_tl_intg_err	44.000s	263.097us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	13.000s	317.513us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	41.000s	780.980us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	19.855us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	104.612us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	44.000s	263.097us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	59.687us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	104.612us	1	1	100.00
		otbn_dmem_err	13.000s	19.855us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	15.556us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	42.633us	1	1	100.00
		otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	51.961us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	104.612us	1	1	100.00
		otbn_dmem_err	13.000s	19.855us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	15.556us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	42.633us	1	1	100.00
		otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	59.687us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	104.612us	1	1	100.00
		otbn_dmem_err	13.000s	19.855us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	15.556us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	42.633us	1	1	100.00
		otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	51.961us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	43.072us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	56.445us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	40.000s	171.189us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	40.000s	171.189us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	83.224us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	58.018us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	18.825us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	18.825us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	19.135us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	51.961us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	51.961us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	51.961us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	57.000s	231.764us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	51.961us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	51.961us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	89.043us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	51.961us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	11.000s	38.054us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.583m	646.394us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	41	95.12

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.85348042370653971055964038631733510455310439624255663860320303661414452922460
      Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19135005 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  19135005 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  19135005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.60353233374575587387602660990249926242765248605188272601204819544099668848481
      Line 103, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 38054399 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 38054399 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  38054399 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  38054399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---