RV_TIMER Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.630s	52.615us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.600s	99.990us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.540s	68.438us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.530s	65.151us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.700s	39.105us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.590s	51.686us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.540s	68.438us	1	1	100.00
		rv_timer_csr_aliasing	1.700s	39.105us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.700s	662.320us	1	1	100.00
V2	disabled	rv_timer_disabled	2.220s	702.831us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	10.255m	2.951s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	10.255m	2.951s	1	1	100.00
V2	stress	rv_timer_stress_all	1.490s	51.414us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.440s	40.532us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.530s	15.178us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.600s	192.633us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.600s	192.633us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.600s	99.990us	1	1	100.00
		rv_timer_csr_rw	1.540s	68.438us	1	1	100.00
		rv_timer_csr_aliasing	1.700s	39.105us	1	1	100.00
		rv_timer_same_csr_outstanding	1.440s	18.930us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.600s	99.990us	1	1	100.00
		rv_timer_csr_rw	1.540s	68.438us	1	1	100.00
		rv_timer_csr_aliasing	1.700s	39.105us	1	1	100.00
		rv_timer_same_csr_outstanding	1.440s	18.930us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.670s	42.192us	1	1	100.00
		rv_timer_tl_intg_err	1.740s	181.150us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.740s	181.150us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	32.100s	3.996ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.490s	14.256us	1	1	100.00
		rv_timer_max	1.620s	39.398us	1	1	100.00
		TOTAL			19	19	100.00