SPI_DEVICE/1R1W Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.981m	25.455ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.810s	19.459us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.630s	309.834us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.320s	702.618us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.590s	237.129us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.710s	39.561us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.630s	309.834us	1	1	100.00
		spi_device_csr_aliasing	10.590s	237.129us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.500s	11.513us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.600s	106.876us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.630s	15.548us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.470s	4.978us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.630s	6.074us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.600s	12.598us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.600s	12.598us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.290s	858.484us	1	1	100.00
		spi_device_tpm_sts_read	1.770s	164.345us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.790s	2.010ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.480s	6.141ms	1	1	100.00
		spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.880s	4.421ms	1	1	100.00
		spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.880s	4.421ms	1	1	100.00
		spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	11.180s	3.143ms	1	1	100.00
		spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	11.180s	3.143ms	1	1	100.00
		spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	11.180s	3.143ms	1	1	100.00
		spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	11.180s	3.143ms	1	1	100.00
		spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	11.180s	3.143ms	1	1	100.00
		spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	14.070s	59.940ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	29.310s	36.944ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	29.310s	36.944ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	29.310s	36.944ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	12.790s	3.612ms	1	1	100.00
		spi_device_read_buffer_direct	4.910s	223.898us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	29.310s	36.944ms	1	1	100.00
		spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.035m	284.209ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.090s	701.628us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.090s	701.628us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.981m	25.455ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.654m	96.179ms	1	1	100.00
V2	stress_all	spi_device_stress_all	37.610s	19.111ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.710s	13.712us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.750s	63.566us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.730s	219.682us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.730s	219.682us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.810s	19.459us	1	1	100.00
		spi_device_csr_rw	2.630s	309.834us	1	1	100.00
		spi_device_csr_aliasing	10.590s	237.129us	1	1	100.00
		spi_device_same_csr_outstanding	3.520s	217.553us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.810s	19.459us	1	1	100.00
		spi_device_csr_rw	2.630s	309.834us	1	1	100.00
		spi_device_csr_aliasing	10.590s	237.129us	1	1	100.00
		spi_device_same_csr_outstanding	3.520s	217.553us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.050s	71.924us	1	1	100.00
		spi_device_tl_intg_err	5.850s	599.575us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.850s	599.575us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.473m	15.730ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.72721350889343776699135465734880199931835017738806410969431547492882989100876
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4258034 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[33])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4258034 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4258034 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[929])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs *xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.73427568617792451942294500686168862972927293884233445062712079393859887265484
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3819188 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4cbb94 [10011001011101110010100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   3864188 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd66e4b [110101100110111001001011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   3892188 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5d1f1e [10111010001111100011110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   3925188 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6e5afb [11011100101101011111011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   4024188 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x72be1e [11100101011111000011110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])