SRAM_CTRL/MAIN Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	13.290s	843.893us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.610s	15.922us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.460s	25.441us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.030s	142.125us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.770s	24.348us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.330s	689.709us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.460s	25.441us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	24.348us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.859m	6.931ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	55.150s	2.822ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.516m	204.436ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.501m	5.532ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	26.021m	113.626ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.435m	117.821ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	16.270s	3.859ms	1	1	100.00
V2	executable	sram_ctrl_executable	16.973m	27.575ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.710s	566.671us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.627m	32.518ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	14.470s	693.166us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	47.220s	4.768ms	1	1	100.00
		sram_ctrl_throughput_w_readback	27.500s	844.863us	1	1	100.00
V2	regwen	sram_ctrl_regwen	11.140m	13.046ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.210s	1.359ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	21.367m	72.200ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.670s	45.037us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.990s	223.342us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.990s	223.342us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.610s	15.922us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	25.441us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	24.348us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.690s	17.502us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.610s	15.922us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	25.441us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	24.348us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.690s	17.502us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.320s	7.741ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.520s	3.589us	0	1	0.00
		sram_ctrl_tl_intg_err	2.820s	395.527us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.520s	3.589us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.820s	395.527us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.140m	13.046ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	11.140m	13.046ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.460s	25.441us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	16.973m	27.575ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	16.973m	27.575ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	16.973m	27.575ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	16.270s	3.859ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.440s	969.371us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.320s	7.741ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.990s	5.059ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	13.290s	843.893us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	13.290s	843.893us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	16.973m	27.575ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.520s	3.589us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	16.270s	3.859ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.520s	3.589us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.520s	3.589us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	13.290s	843.893us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.520s	3.589us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	23.510s	1.160ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.46533985716773009771091449765652552980590620418853313357199476053447040373697
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3588557 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3588557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---