SRAM_CTRL/RET Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.410s	350.894us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.520s	17.370us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.490s	57.722us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.970s	130.618us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.470s	20.371us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.060s	112.870us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.490s	57.722us	1	1	100.00
		sram_ctrl_csr_aliasing	1.470s	20.371us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.890s	878.729us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.800s	163.460us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.889m	65.913ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.542m	10.836ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	58.130s	10.385ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.235m	2.384ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.260s	2.553ms	1	1	100.00
V2	executable	sram_ctrl_executable	11.853m	32.396ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.980s	4.173ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.821m	64.560ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.870s	37.549us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.760s	57.102us	1	1	100.00
		sram_ctrl_throughput_w_readback	37.420s	1.175ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	20.125m	69.720ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.790s	29.754us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	19.567m	11.623ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.500s	19.456us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.240s	120.961us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.240s	120.961us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.520s	17.370us	1	1	100.00
		sram_ctrl_csr_rw	1.490s	57.722us	1	1	100.00
		sram_ctrl_csr_aliasing	1.470s	20.371us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.730s	15.175us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.520s	17.370us	1	1	100.00
		sram_ctrl_csr_rw	1.490s	57.722us	1	1	100.00
		sram_ctrl_csr_aliasing	1.470s	20.371us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.730s	15.175us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.490s	510.312us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.530s	17.694us	0	1	0.00
		sram_ctrl_tl_intg_err	2.030s	263.866us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.530s	17.694us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.030s	263.866us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.125m	69.720ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.125m	69.720ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.490s	57.722us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	11.853m	32.396ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	11.853m	32.396ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	11.853m	32.396ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.260s	2.553ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.830s	52.158us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.490s	510.312us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.940s	34.554us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.410s	350.894us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.410s	350.894us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	11.853m	32.396ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.530s	17.694us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.260s	2.553ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.530s	17.694us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.530s	17.694us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.410s	350.894us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.530s	17.694us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	28.110s	1.337ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.6374127770561366239159540160982049146342486637255972030929650320604747066341
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  52157754 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  52157754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.20947808851521774194693724732884185729120614708255286588207664620267836071957
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  17694432 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  17694432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---