UART Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.020s	288.149us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.470s	15.162us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.550s	16.615us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.020s	96.088us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.690s	82.557us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.850s	51.369us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.550s	16.615us	1	1	100.00
		uart_csr_aliasing	1.690s	82.557us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	8.070s	6.128ms	1	1	100.00
V2	parity	uart_smoke	2.020s	288.149us	1	1	100.00
		uart_tx_rx	8.070s	6.128ms	1	1	100.00
V2	parity_error	uart_intr	22.190s	18.083ms	1	1	100.00
		uart_rx_parity_err	41.550s	32.439ms	1	1	100.00
V2	watermark	uart_tx_rx	8.070s	6.128ms	1	1	100.00
		uart_intr	22.190s	18.083ms	1	1	100.00
V2	fifo_full	uart_fifo_full	34.680s	114.735ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	33.240s	27.894ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	8.750s	19.887ms	1	1	100.00
V2	rx_frame_err	uart_intr	22.190s	18.083ms	1	1	100.00
V2	rx_break_err	uart_intr	22.190s	18.083ms	1	1	100.00
V2	rx_timeout	uart_intr	22.190s	18.083ms	1	1	100.00
V2	perf	uart_perf	2.874m	19.140ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.210s	1.422ms	1	1	100.00
V2	line_loopback	uart_loopback	2.210s	1.422ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.065m	98.499ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	31.510s	34.414ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.420s	587.742us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	9.400s	6.423ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.417m	104.383ms	1	1	100.00
V2	stress_all	uart_stress_all	20.480s	32.301ms	1	1	100.00
V2	alert_test	uart_alert_test	1.460s	34.527us	1	1	100.00
V2	intr_test	uart_intr_test	1.370s	12.917us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.240s	159.814us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.240s	159.814us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.470s	15.162us	1	1	100.00
		uart_csr_rw	1.550s	16.615us	1	1	100.00
		uart_csr_aliasing	1.690s	82.557us	1	1	100.00
		uart_same_csr_outstanding	1.520s	132.932us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.470s	15.162us	1	1	100.00
		uart_csr_rw	1.550s	16.615us	1	1	100.00
		uart_csr_aliasing	1.690s	82.557us	1	1	100.00
		uart_same_csr_outstanding	1.520s	132.932us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.710s	48.612us	1	1	100.00
		uart_tl_intg_err	1.970s	76.184us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.970s	76.184us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	41.070s	9.948ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00