CHIP Simulation Results

Wednesday May 07 2025 17:02:37 UTC

GitHub Revision: `3add6b6`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.049m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.049m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	31.362s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	13.898s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	14.772s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.834m	6.850ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.834m	6.850ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.834m	6.850ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	41.390s	10.280us	0	1	0.00
		chip_sw_example_manufacturer	2.583m		0	1	0.00
		chip_sw_example_concurrency	4.115m	5.641ms	1	1	100.00
		chip_sw_uart_smoketest_signed	38.189s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	18.130s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	11.080s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	11.080s		0	1	0.00
V1	xbar_smoke	xbar_smoke	21.890s	61.617us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.015m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.624m	8.193ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.486m	4.653ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	16.704s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	14.002s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.121s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	13.578s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.450s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.450s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.453m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.386m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.606m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.606m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.401m	4.423ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.077m	3.263ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.451m	14.041ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.057s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.417s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	16.900m	24.875ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.922m	4.434ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.636m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.636m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.098s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.571m	5.102ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.571m	5.102ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.253m	18.022ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.315m	5.205ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.507m	4.454ms	1	1	100.00
		chip_sw_aes_idle	3.942m	5.299ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.291m	3.834ms	1	1	100.00
		chip_sw_kmac_idle	4.101m	4.877ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.028s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.650s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.929s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.057s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.779s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.441s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.063s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.349s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.311s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.777s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.713s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.779s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.441s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.063s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.349s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.311s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.777s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.713s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.835s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.377m	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	57.650s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.190s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.800s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.234s		0	1	0.00
		chip_sw_clkmgr_jitter	3.358m	4.127ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.831m	3.470ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	14.064s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	47.620s	10.380us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.240s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	47.340s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	45.680s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	51.390s	10.180us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	10.984s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.096s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.950s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.001s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.447m	14.796ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.102m	13.350ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.571m	5.102ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.177s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.102m	13.350ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.550s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.454s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	14.287s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	13.892s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.335s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.447m	14.796ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.451m	14.041ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	22.588m	20.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.102m	7.731ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.176m	6.799ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.441m	3.719ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.447m	14.796ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.116s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.379s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.447m	14.796ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.288s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.176m	6.799ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.068s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.058s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.481s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.750s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.571s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.932s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.379s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.936s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.365s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.936s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.936s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.936s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.896m	9.440ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.898s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.184s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.770s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.103s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.936s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.428m	8.225ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.654m	12.971ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	14.281s		0	1	0.00
		chip_prim_tl_access	9.092m	18.745ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.779s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.441s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.063s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.349s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.311s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.777s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.713s		0	1	0.00
		chip_rv_dm_lc_disabled	16.900m	24.875ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.717m	5.040ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.377m	10.360us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.566m	3.443ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.942m	5.299ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.404m	5.211ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	57.650s	10.120us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.291m	3.834ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.877m	5.008ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.436m	4.850ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	52.800s	10.280us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.428m	8.225ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.936s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.640s	10.240us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.589m	5.000ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.101m	4.877ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.995s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.995s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.392s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.562m	4.907ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.446s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.428m	8.225ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.190s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.925s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.835s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.507m	4.454ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.507m	4.454ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.507m	4.454ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.322m	6.175ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.654m	12.971ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.654m	12.971ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.135m	6.600ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.234s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.281s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.447m	14.796ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.606m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.936s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.322m	6.175ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.428m	8.225ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.135m	6.600ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.684m	5.728ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.322m	6.175ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.428m	8.225ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.135m	6.600ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.684m	5.728ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.936s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.203s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.365s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.898s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.184s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.770s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.103s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.936s		0	1	0.00
		chip_prim_tl_access	9.092m	18.745ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.092m	18.745ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.064s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.913s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.096s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.835s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.377m	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	57.650s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.190s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.800s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.234s		0	1	0.00
		chip_sw_clkmgr_jitter	3.358m	4.127ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.023m	5.986ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.023m	5.986ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.358m	4.000ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.240m	4.219ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.161m	5.922ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.124m	6.779ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.107m	4.918ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.160m	3.231ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.684m	5.728ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	22.588m	20.016ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	22.588m	20.016ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.643m	4.160ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.800m	5.545ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.148m	3.542ms	1	1	100.00
		chip_sw_csrng_smoketest	3.765m	4.862ms	1	1	100.00
		chip_sw_gpio_smoketest	3.620m	4.078ms	1	1	100.00
		chip_sw_hmac_smoketest	4.379m	4.837ms	1	1	100.00
		chip_sw_kmac_smoketest	4.273m	5.066ms	1	1	100.00
		chip_sw_otbn_smoketest	4.011m	4.245ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.098m	4.380ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.847m	3.613ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.713m	5.285ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.167m	5.307ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.344m	5.567ms	1	1	100.00
		chip_sw_uart_smoketest	3.329m	4.750ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	20.399s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	38.189s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.015m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.234s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.967m	4.733ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.589m	5.655ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.385m	6.354ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.451m	3.359ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	10.451s		0	1	0.00
		chip_rv_dm_lc_disabled	16.900m	24.875ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.471s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.489s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.461s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.128s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	10.451s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.844s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.153s		0	1	0.00
		rom_volatile_raw_unlock	11.026s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	15.059s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	40.650s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.029m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.361m	4.598ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.361m	4.598ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	11.080s		0	1	0.00
		chip_same_csr_outstanding	11.140s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	11.080s		0	1	0.00
		chip_same_csr_outstanding	11.140s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	48.790s	41.461us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.710s	11.882us	1	1	100.00
		xbar_smoke_large_delays	4.343m	2.186ms	1	1	100.00
		xbar_smoke_slow_rsp	6.037m	2.231ms	1	1	100.00
		xbar_random_zero_delays	31.800s	33.269us	1	1	100.00
		xbar_random_large_delays	15.010m	7.637ms	1	1	100.00
		xbar_random_slow_rsp	33.602m	12.964ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.507m	176.096us	1	1	100.00
		xbar_error_and_unmapped_addr	30.760s	69.944us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.928m	385.613us	1	1	100.00
		xbar_error_and_unmapped_addr	30.760s	69.944us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.511m	119.441us	1	1	100.00
		xbar_access_same_device_slow_rsp	38.778m	15.233ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	11.760s	9.520us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	25.690m	4.232ms	1	1	100.00
		xbar_stress_all_with_error	12.052m	1.938ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	17.012m	876.925us	1	1	100.00
		xbar_stress_all_with_reset_error	4.606m	131.740us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.204s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.028s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.489s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.519s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.574s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.030s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.666s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.135s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.336s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.280s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.268s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.029s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.580s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.411s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.862s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	13.033s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.025s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.266s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.342s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.427s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.123s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.637s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.281s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.255s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.308s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.633s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.675s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.395s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.419s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.708s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.945s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.302s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.869s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.355s		0	1	0.00
		rom_e2e_asm_init_dev	11.885s		0	1	0.00
		rom_e2e_asm_init_prod	11.631s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.709s		0	1	0.00
		rom_e2e_asm_init_rma	11.821s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.020s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.334s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.013s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.355s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.079m	5.691ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.915m	4.026ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.133s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.467s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.875s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	14.575s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.447m	14.796ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.265s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.991m	15.610ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	16.129s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.362s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.133s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.467s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.875s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.350s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.633s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.830s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.155m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.550m	16.427ms	1	1	100.00
		chip_plic_all_irqs_0	8.099m	7.087ms	1	1	100.00
		chip_plic_all_irqs_10	8.801m	6.037ms	1	1	100.00
		chip_sw_dma_inline_hashing	3.874m	4.061ms	1	1	100.00
		chip_sw_dma_abort	3.887m	5.363ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.994s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.076s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.373s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.187s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.499s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.842s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.220s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.964s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.417s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.322s		0	1	0.00
		chip_sw_mbx_smoketest	4.427m	5.665ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 140 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.98459943011440487877776297021942129069113940308750936791748500506555031255202
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (847de7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 137.704s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.38261691796630531812000538219229898315935414338669413336808160296494490361391
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (768c7d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 86.178s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.65908179243054746854378521570615843138234411932778794379206698618316496526685
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (d74e0e)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 77.148s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.69745576949554923681224613323989423779961295636465241603139095156028013103333
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (2d9baf)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 73.199s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.92963015320908742305012583931799118531459817443638577350964723424348554929249
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (4e4d59)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 50.986s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 135 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.69025815756672164847176110726373399327982288533243846004127678913214097952887
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.49910376708653901521365858890636403784423251599056734386605300449908151404805
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.86628110055795021389023494292361796433373098736025329190387166397065727899966
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.83344187732684066307291432282938267148709716554008481656069805816302211574638
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.1259826077650937613054700754878987114073224325602856669396949702121041511977
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.3860498930561014619458260766058422191441618653446176956232391170863260960162
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.69270253969148774485447274287138630125513164140047293190392418161603350432409
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.105455985625399464358195695340581981910015399608282134768342082383172426933056
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.7863630869982678546479688539682712242617009963791188935794554227981952593949
Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.383928 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.383928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.21591170031615345096774045366563595063884217960447935035198909842123312711359
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.476296 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.476296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.55801981468200660868647525551089212645920159923650268524600209856741024407825
Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18021.963829 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18021.963829 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.48206311679369436812560623455372375512513919816070627362184965252247352160384
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8224.663124 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (6088622579925518697823009072041895785308455210934993045511552825746597481545 [0xd7609cb3a0baa527756c9cf27743de1ce1585161114cde4bc565b1c1c5e0c49] vs 77587063805600484773885911176020637482549324759974575646885330167850573301587 [0xab88b8ced0aadf25ffd2efe9ba5b6f7dbfbeb8bb49b840ee5fe5b43dad210753])
  UVM_INFO @ 8224.663124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.19703541758562116592869458838432069894261929921459689371553857944024212441793
Line 464, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9439.698216 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (46306648132170947003198614065813380165122058565662661291521531232421815866593 [0x6660a250b2173670ab2d475f1c8c31592cab0c39f6a9f1de6026401252e554e1] vs 41138586431857684288479265168224698237598082165731238905280833452021530998989 [0x5af39d623c7fe022fb51194ac9ddfee015823c863b97582920a7a9171fafb8cd])
  UVM_INFO @ 9439.698216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.108052339650788595979541280015693502209630198126528939380949322827496665863521
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4422.564303 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h3fd92e61  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h0  a_user: 'h26962  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4422.564303 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.72316739324491034293453980003098205751102460775424846333425248414313045064471
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3262.572202 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h156dc0fd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h1  a_user: 'h248c4  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3262.572202 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.70419665777130689064682115414566198652159501325822620182078349232275449369601
    Line 623, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.46888838182402593211060419970739827385651975281009877133861526130821003471637
    Line 452, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4652.844520 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4652.844520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.114216695014745043867578403286559497151045456817600624812015697010411642292355
    Line 657, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6798.545096 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6798.545096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.55494230454787025098008569671283462731864068901872387765761625248004784401265
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4000.148842 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4000.148842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.23985013073848844205852523527264817477828873406165217736213710613162123302772
    Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4219.431690 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4219.431690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.35718103439486778178956482573250789453031489055763446852640005811435788058129
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5101.731860 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5101.731860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.99530923736273807106699842391464469053986002623035669096223084325654781436385
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6778.573380 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6778.573380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.66531186963954259425435059560292146020815299354632296664521144225883013539918
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35968) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.10309885256441566420986214862725727363395512220406500903692891343508806142091
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4598.019040 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35968) { a_addr: 'h4037c  a_data: 'hf6a405ce  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h1a14f  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4598.019040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.25738512644928770064523885826752824659144385687486503913261378044862906300416
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14040.581928 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14040.581928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.83935292694978431891920440333020953432245069250688695750009973787839209928022
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.15252113758205921190074163381673496722561607034309790638812869572410811099218
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5362.711142 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5362.711142 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```