DMA Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 dma_memory_smoke dma_memory_smoke 9.000s 1.239ms 1 1 100.00
V1 dma_handshake_smoke dma_handshake_smoke 11.000s 1.713ms 1 1 100.00
V1 dma_generic_smoke dma_generic_smoke 9.000s 1.417ms 1 1 100.00
V1 csr_hw_reset dma_csr_hw_reset 4.000s 23.950us 1 1 100.00
V1 csr_rw dma_csr_rw 4.000s 54.785us 1 1 100.00
V1 csr_bit_bash dma_csr_bit_bash 8.000s 153.584us 1 1 100.00
V1 csr_aliasing dma_csr_aliasing 7.000s 4.997ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset dma_csr_mem_rw_with_rand_reset 5.000s 30.427us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr dma_csr_rw 4.000s 54.785us 1 1 100.00
dma_csr_aliasing 7.000s 4.997ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 dma_memory_region_lock dma_memory_region_lock 2.133m 8.557ms 1 1 100.00
V2 dma_handshake_stress dma_handshake_stress 37.083m 228.302ms 1 1 100.00
V2 dma_memory_stress dma_memory_stress 4.800m 90.317ms 1 1 100.00
V2 dma_generic_stress dma_generic_stress 0 1 0.00
V2 dma_handshake_mem_buffer_overflow dma_handshake_stress 37.083m 228.302ms 1 1 100.00
V2 dma_abort dma_abort 15.000s 15.669ms 1 1 100.00
V2 dma_stress_all dma_stress_all 6.517m 64.530ms 1 1 100.00
V2 intr_test dma_intr_test 4.000s 44.046us 1 1 100.00
V2 tl_d_oob_addr_access dma_tl_errors 5.000s 50.846us 1 1 100.00
V2 tl_d_illegal_access dma_tl_errors 5.000s 50.846us 1 1 100.00
V2 tl_d_outstanding_access dma_csr_hw_reset 4.000s 23.950us 1 1 100.00
dma_csr_rw 4.000s 54.785us 1 1 100.00
dma_csr_aliasing 7.000s 4.997ms 1 1 100.00
dma_same_csr_outstanding 5.000s 503.925us 1 1 100.00
V2 tl_d_partial_access dma_csr_hw_reset 4.000s 23.950us 1 1 100.00
dma_csr_rw 4.000s 54.785us 1 1 100.00
dma_csr_aliasing 7.000s 4.997ms 1 1 100.00
dma_same_csr_outstanding 5.000s 503.925us 1 1 100.00
V2 TOTAL 8 9 88.89
V2S dma_illegal_addr_range dma_mem_enabled 33.000s 505.109us 1 1 100.00
dma_generic_stress 0 1 0.00
dma_handshake_stress 37.083m 228.302ms 1 1 100.00
V2S tl_intg_err dma_tl_intg_err 6.000s 435.619us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests dma_short_transfer 1.533m 5.029ms 1 1 100.00
dma_longer_transfer 5.000s 72.979us 1 1 100.00
TOTAL 20 21 95.24

Failure Buckets