EDN Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.850s 17.512us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.690s 43.618us 1 1 100.00
V1 csr_rw edn_csr_rw 1.640s 48.630us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.750s 188.797us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.660s 51.906us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.330s 160.899us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.640s 48.630us 1 1 100.00
edn_csr_aliasing 1.660s 51.906us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.980s 37.677us 1 1 100.00
V2 csrng_commands edn_genbits 1.980s 37.677us 1 1 100.00
V2 genbits edn_genbits 1.980s 37.677us 1 1 100.00
V2 interrupts edn_intr 1.720s 24.794us 1 1 100.00
V2 alerts edn_alert 2.010s 447.260us 1 1 100.00
V2 errs edn_err 1.740s 21.787us 1 1 100.00
V2 disable edn_disable 1.700s 18.400us 1 1 100.00
edn_disable_auto_req_mode 1.810s 146.955us 1 1 100.00
V2 stress_all edn_stress_all 4.860s 551.865us 1 1 100.00
V2 intr_test edn_intr_test 1.750s 27.055us 1 1 100.00
V2 alert_test edn_alert_test 1.950s 85.036us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.630s 105.194us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.630s 105.194us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.690s 43.618us 1 1 100.00
edn_csr_rw 1.640s 48.630us 1 1 100.00
edn_csr_aliasing 1.660s 51.906us 1 1 100.00
edn_same_csr_outstanding 2.070s 206.063us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.690s 43.618us 1 1 100.00
edn_csr_rw 1.640s 48.630us 1 1 100.00
edn_csr_aliasing 1.660s 51.906us 1 1 100.00
edn_same_csr_outstanding 2.070s 206.063us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.670s 2.154ms 1 1 100.00
edn_tl_intg_err 2.810s 276.043us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.620s 121.300us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.010s 447.260us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.670s 2.154ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.670s 2.154ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.670s 2.154ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.670s 2.154ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.010s 447.260us 1 1 100.00
edn_sec_cm 7.670s 2.154ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.010s 447.260us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.810s 276.043us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets