HMAC Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 11.010s 2.185ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.670s 136.935us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.950s 18.961us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.370s 2.841ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.160s 449.960us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 8.806m 52.397ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.950s 18.961us 1 1 100.00
hmac_csr_aliasing 7.160s 449.960us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 30.070s 3.244ms 1 1 100.00
V2 back_pressure hmac_back_pressure 36.260s 4.773ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.772m 7.386ms 1 1 100.00
hmac_test_sha384_vectors 5.170m 97.948ms 1 1 100.00
hmac_test_sha512_vectors 5.655m 187.562ms 1 1 100.00
hmac_test_hmac256_vectors 8.930s 1.119ms 1 1 100.00
hmac_test_hmac384_vectors 10.100s 3.616ms 1 1 100.00
hmac_test_hmac512_vectors 10.150s 1.125ms 1 1 100.00
V2 burst_wr hmac_burst_wr 11.750s 911.874us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 27.510s 823.729us 1 1 100.00
V2 error hmac_error 19.070s 8.397ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.342m 6.546ms 1 1 100.00
V2 save_and_restore hmac_smoke 11.010s 2.185ms 1 1 100.00
hmac_long_msg 30.070s 3.244ms 1 1 100.00
hmac_back_pressure 36.260s 4.773ms 1 1 100.00
hmac_datapath_stress 27.510s 823.729us 1 1 100.00
hmac_burst_wr 11.750s 911.874us 1 1 100.00
hmac_stress_all 2.647m 21.696ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 11.010s 2.185ms 1 1 100.00
hmac_long_msg 30.070s 3.244ms 1 1 100.00
hmac_back_pressure 36.260s 4.773ms 1 1 100.00
hmac_datapath_stress 27.510s 823.729us 1 1 100.00
hmac_wipe_secret 1.342m 6.546ms 1 1 100.00
hmac_test_sha256_vectors 3.772m 7.386ms 1 1 100.00
hmac_test_sha384_vectors 5.170m 97.948ms 1 1 100.00
hmac_test_sha512_vectors 5.655m 187.562ms 1 1 100.00
hmac_test_hmac256_vectors 8.930s 1.119ms 1 1 100.00
hmac_test_hmac384_vectors 10.100s 3.616ms 1 1 100.00
hmac_test_hmac512_vectors 10.150s 1.125ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 11.010s 2.185ms 1 1 100.00
hmac_long_msg 30.070s 3.244ms 1 1 100.00
hmac_back_pressure 36.260s 4.773ms 1 1 100.00
hmac_datapath_stress 27.510s 823.729us 1 1 100.00
hmac_burst_wr 11.750s 911.874us 1 1 100.00
hmac_error 19.070s 8.397ms 1 1 100.00
hmac_wipe_secret 1.342m 6.546ms 1 1 100.00
hmac_test_sha256_vectors 3.772m 7.386ms 1 1 100.00
hmac_test_sha384_vectors 5.170m 97.948ms 1 1 100.00
hmac_test_sha512_vectors 5.655m 187.562ms 1 1 100.00
hmac_test_hmac256_vectors 8.930s 1.119ms 1 1 100.00
hmac_test_hmac384_vectors 10.100s 3.616ms 1 1 100.00
hmac_test_hmac512_vectors 10.150s 1.125ms 1 1 100.00
hmac_stress_all 2.647m 21.696ms 1 1 100.00
V2 stress_all hmac_stress_all 2.647m 21.696ms 1 1 100.00
V2 alert_test hmac_alert_test 1.470s 36.349us 1 1 100.00
V2 intr_test hmac_intr_test 1.730s 23.168us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.020s 552.097us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.020s 552.097us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.670s 136.935us 1 1 100.00
hmac_csr_rw 1.950s 18.961us 1 1 100.00
hmac_csr_aliasing 7.160s 449.960us 1 1 100.00
hmac_same_csr_outstanding 1.880s 23.133us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.670s 136.935us 1 1 100.00
hmac_csr_rw 1.950s 18.961us 1 1 100.00
hmac_csr_aliasing 7.160s 449.960us 1 1 100.00
hmac_same_csr_outstanding 1.880s 23.133us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.900s 350.589us 1 1 100.00
hmac_tl_intg_err 3.310s 191.459us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.310s 191.459us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 11.010s 2.185ms 1 1 100.00
V3 stress_reset hmac_stress_reset 4.480s 92.166us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.094m 5.031ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.370s 43.618us 1 1 100.00
TOTAL 28 28 100.00