I2C Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	24.760s	6.768ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.430s	1.155ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.560s	50.836us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.870s	29.835us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.950s	1.093ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.870s	118.093us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.680s	230.764us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.870s	29.835us	1	1	100.00
		i2c_csr_aliasing	2.870s	118.093us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	18.730s	1.227ms	1	1	100.00
V2	host_stress_all	i2c_host_stress_all			0	1	0.00
V2	host_maxperf	i2c_host_perf	47.530s	28.334ms	1	1	100.00
V2	host_override	i2c_host_override	1.700s	67.937us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.077m	3.813ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.044m	2.935ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.130s	559.827us	1	1	100.00
		i2c_host_fifo_fmt_empty	18.730s	4.068ms	1	1	100.00
		i2c_host_fifo_reset_rx	6.950s	194.137us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	44.990s	9.962ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.480s	12.453ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.540s	488.504us	1	1	100.00
V2	target_glitch	i2c_target_glitch	9.180s	7.502ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	21.510s	7.440ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.230s	1.127ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	20.640s	1.629ms	1	1	100.00
		i2c_target_intr_smoke	5.780s	2.180ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.610s	308.539us	1	1	100.00
		i2c_target_fifo_reset_tx	2.540s	582.841us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	4.770s	30.481ms	1	1	100.00
		i2c_target_stress_rd	20.640s	1.629ms	1	1	100.00
		i2c_target_intr_stress_wr	19.740s	6.831ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.940s	1.569ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	48.790s	3.855ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.900s	718.110us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	10.550s	10.100ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.970s	331.171us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.080s	128.160us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	47.530s	28.334ms	1	1	100.00
		i2c_host_perf_precise	31.200s	24.879ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.480s	12.453ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.110s	259.466us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.660s	1.666ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.850s	515.824us	1	1	100.00
		i2c_target_nack_txstretch	2.090s	675.812us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	10.800s	1.642ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.540s	530.991us	1	1	100.00
V2	alert_test	i2c_alert_test	1.670s	48.800us	1	1	100.00
V2	intr_test	i2c_intr_test	1.780s	55.938us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.600s	182.041us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.600s	182.041us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.560s	50.836us	1	1	100.00
		i2c_csr_rw	1.870s	29.835us	1	1	100.00
		i2c_csr_aliasing	2.870s	118.093us	1	1	100.00
		i2c_same_csr_outstanding	1.670s	37.364us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.560s	50.836us	1	1	100.00
		i2c_csr_rw	1.870s	29.835us	1	1	100.00
		i2c_csr_aliasing	2.870s	118.093us	1	1	100.00
		i2c_same_csr_outstanding	1.670s	37.364us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.500s	303.955us	1	1	100.00
		i2c_sec_cm	1.930s	394.772us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.500s	303.955us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.460s	1.596ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.930s	519.776us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.590s	3.433ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.86870024481781533364188744292972114352171892687980937658796749424832491033486
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1595883680 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1595883680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.97057838994267390534506891333997619239253762682526778999644811874107774556315
      Line 103, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3432955843 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3432955843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.109507258726428055772654055451666449056294709562602528418606682832274732606912
      Log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.1598231684610767322491824916539329935622172974991142139755376727878762626131
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 519775946 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 12 [0xc])
        UVM_INFO @ 519775946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.90257964018900956681322924490068427613873537690391046774288715812189151562865
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10099910438 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10099910438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---