| V1 |
smoke |
keymgr_dpe_smoke |
7.170s |
762.446us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.960s |
42.083us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.690s |
76.447us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
5.030s |
436.106us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
3.020s |
46.860us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
2.390s |
332.865us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.690s |
76.447us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.020s |
46.860us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.540s |
17.619us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.690s |
23.923us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.980s |
126.235us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.980s |
126.235us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.960s |
42.083us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.690s |
76.447us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.020s |
46.860us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.930s |
64.965us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.960s |
42.083us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.690s |
76.447us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.020s |
46.860us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.930s |
64.965us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
6.190s |
429.607us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.340s |
384.698us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.300s |
418.631us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.300s |
418.631us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.300s |
418.631us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.300s |
418.631us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
5.180s |
300.383us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
6.190s |
429.607us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
6.190s |
429.607us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |