KMAC/MASKED Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	9.430s	272.825us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.710s	52.312us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.080s	112.234us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.540s	2.557ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.810s	72.353us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.610s	83.879us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.080s	112.234us	1	1	100.00
		kmac_csr_aliasing	3.810s	72.353us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.690s	11.289us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.000s	160.038us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	15.605m	515.806ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.537m	21.053ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.830s	5.644ms	1	1	100.00
		kmac_test_vectors_sha3_256	31.571m	89.489ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.960s	6.342ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.490s	4.347ms	1	1	100.00
		kmac_test_vectors_shake_128	35.575m	358.800ms	1	1	100.00
		kmac_test_vectors_shake_256	1.702m	5.490ms	1	1	100.00
		kmac_test_vectors_kmac	2.920s	87.895us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.850s	129.487us	1	1	100.00
V2	sideload	kmac_sideload	3.270m	12.981ms	1	1	100.00
V2	app	kmac_app	4.828m	57.242ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.446m	8.563ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.376m	13.332ms	1	1	100.00
V2	error	kmac_error	31.400s	1.633ms	1	1	100.00
V2	key_error	kmac_key_error	6.040s	2.789ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.430s	32.995us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.020s	39.781us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.640s	16.898us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	33.920s	14.755ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.360s	38.494us	1	1	100.00
V2	stress_all	kmac_stress_all	12.817m	28.932ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.750s	21.271us	1	1	100.00
V2	alert_test	kmac_alert_test	1.760s	24.825us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.000s	202.021us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.000s	202.021us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.710s	52.312us	1	1	100.00
		kmac_csr_rw	2.080s	112.234us	1	1	100.00
		kmac_csr_aliasing	3.810s	72.353us	1	1	100.00
		kmac_same_csr_outstanding	3.510s	119.128us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.710s	52.312us	1	1	100.00
		kmac_csr_rw	2.080s	112.234us	1	1	100.00
		kmac_csr_aliasing	3.810s	72.353us	1	1	100.00
		kmac_same_csr_outstanding	3.510s	119.128us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.070s	67.450us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.070s	67.450us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.070s	67.450us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.070s	67.450us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.220s	49.232us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	58.380s	18.531ms	1	1	100.00
		kmac_tl_intg_err	4.570s	422.902us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.570s	422.902us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.360s	38.494us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	9.430s	272.825us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.270m	12.981ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.070s	67.450us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	58.380s	18.531ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	58.380s	18.531ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	58.380s	18.531ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	9.430s	272.825us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.360s	38.494us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	58.380s	18.531ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.942m	2.580ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	9.430s	272.825us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.585m	7.189ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.74612993738707371431064849376597361491078357044725378489896268149684321398494
      Line 159, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7188884756 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7188884756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.96361915671918639273104915994669123182243621870101376102575905605989043999537
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
        UVM_ERROR @  49231666 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
        UVM_INFO @  49231666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---