KMAC/UNMASKED Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	38.320s	39.544ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.720s	111.578us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.610s	65.300us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.250s	515.797us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.920s	3.704ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.370s	76.628us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.610s	65.300us	1	1	100.00
		kmac_csr_aliasing	7.920s	3.704ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.520s	14.990us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.040s	21.409us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	19.230m	36.608ms	1	1	100.00
V2	burst_write	kmac_burst_write	14.480s	522.369us	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.960s	11.676ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.310s	2.348ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.784m	143.922ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.030s	5.293ms	1	1	100.00
		kmac_test_vectors_shake_128	2.515m	13.751ms	1	1	100.00
		kmac_test_vectors_shake_256	27.172m	92.059ms	1	1	100.00
		kmac_test_vectors_kmac	2.560s	477.088us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.270s	94.921us	1	1	100.00
V2	sideload	kmac_sideload	1.494m	30.939ms	1	1	100.00
V2	app	kmac_app	2.191m	31.888ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.751m	56.625ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.975m	11.385ms	1	1	100.00
V2	error	kmac_error	1.375m	5.038ms	1	1	100.00
V2	key_error	kmac_key_error	5.640s	2.618ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.970s	236.266us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.060s	1.085ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.860s	818.351us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	9.550s	1.101ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.250s	133.593us	1	1	100.00
V2	stress_all	kmac_stress_all	37.610s	8.149ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.690s	53.920us	1	1	100.00
V2	alert_test	kmac_alert_test	1.600s	16.596us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.070s	61.540us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.070s	61.540us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.720s	111.578us	1	1	100.00
		kmac_csr_rw	1.610s	65.300us	1	1	100.00
		kmac_csr_aliasing	7.920s	3.704ms	1	1	100.00
		kmac_same_csr_outstanding	2.740s	345.797us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.720s	111.578us	1	1	100.00
		kmac_csr_rw	1.610s	65.300us	1	1	100.00
		kmac_csr_aliasing	7.920s	3.704ms	1	1	100.00
		kmac_same_csr_outstanding	2.740s	345.797us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.970s	416.903us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.970s	416.903us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.970s	416.903us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.970s	416.903us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.590s	22.396us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	37.650s	3.310ms	1	1	100.00
		kmac_tl_intg_err	2.850s	433.268us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.850s	433.268us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.250s	133.593us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	38.320s	39.544ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.494m	30.939ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.970s	416.903us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	37.650s	3.310ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	37.650s	3.310ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	37.650s	3.310ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	38.320s	39.544ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.250s	133.593us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	37.650s	3.310ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.449m	30.685ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	38.320s	39.544ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	42.420s	2.084ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.61332761010004936640632399504274939463330826622021810092881783097464802062938
      Line 101, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2083763560 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2083763560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.35801997801576857189457843171701518753105642250778396690802279344902320635098
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @  22396443 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @  22396443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---