122442b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 26.000s | 2.061ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 5.000s | 54.455us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 5.000s | 34.046us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 5.000s | 211.692us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 5.000s | 22.151us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 896.480ns | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 5.000s | 34.046us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 5.000s | 22.151us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 17.000s | 2.361ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 1.817m | 2.528ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 10.000s | 659.994us | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 40.133us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 5.000s | 993.603ns | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 5.000s | 993.603ns | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 5.000s | 54.455us | 1 | 1 | 100.00 |
| mbx_csr_rw | 5.000s | 34.046us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 5.000s | 22.151us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 5.000s | 27.025us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 5.000s | 54.455us | 1 | 1 | 100.00 |
| mbx_csr_rw | 5.000s | 34.046us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 5.000s | 22.151us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 5.000s | 27.025us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 5.000s | 22.335us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 5.000s | 17.986us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.105074612592411954089796259381753797920528413195209415055507191381017027142882
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 993603 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x8385bf54 a_data = 0xe21d7413 a_mask = 0x3 a_size = 0x2 a_param = 0x0 a_source = 0x4a a_opcode = PutFullData a_user = 0x2561b d_data = 0xa395d434 d_size = 0x1 d_param = 0x0 d_source = 0xb6 d_opcode = AccessAck d_error = 0 d_user = 1111111101101 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 993603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.94323729022219103876806626111739061324062693234088540590791154462972983483976
Line 92, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 17985752 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x6021e7b0 a_data = 0x77d460d6 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xb1 a_opcode = Get a_user = 0x27e32 d_data = 0x37ffbe43 d_size = 0x3 d_param = 0x0 d_source = 0x4b d_opcode = AccessAckData d_error = 0 d_user = 11011011001 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 17985752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.94481726671533736896087368276326133728360011796593064754221301080699802407223
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 896480 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xa8f2efd8 a_data = 0xdab5cdb5 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x97 a_opcode = PutPartialData a_user = 0x1f343 d_data = 0x2941b78a d_size = 0x2 d_param = 0x0 d_source = 0xc8 d_opcode = AccessAck d_error = 0 d_user = 10001011101011 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 896480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---