ROM_CTRL/32KB Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.050s	144.974us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.760s	217.458us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.940s	300.926us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.560s	127.652us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.170s	453.510us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.680s	617.488us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.940s	300.926us	1	1	100.00
		rom_ctrl_csr_aliasing	4.170s	453.510us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.650s	1.074ms	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.150s	213.072us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.160s	753.100us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	10.020s	5.536ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.470s	218.110us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.400s	1.076ms	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	7.380s	335.957us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	7.380s	335.957us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.760s	217.458us	1	1	100.00
		rom_ctrl_csr_rw	4.940s	300.926us	1	1	100.00
		rom_ctrl_csr_aliasing	4.170s	453.510us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.610s	557.657us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.760s	217.458us	1	1	100.00
		rom_ctrl_csr_rw	4.940s	300.926us	1	1	100.00
		rom_ctrl_csr_aliasing	4.170s	453.510us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.610s	557.657us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	12.690s	403.889us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.569m	534.627us	1	1	100.00
		rom_ctrl_tl_intg_err	22.380s	874.582us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.569m	534.627us	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.569m	534.627us	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.569m	534.627us	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.569m	534.627us	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.050s	144.974us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.050s	144.974us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.050s	144.974us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	22.380s	874.582us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
		rom_ctrl_kmac_err_chk	7.470s	218.110us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	18.160s	452.598us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	12.690s	403.889us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.569m	534.627us	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	38.350s	2.946ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:695) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.65244745211341632703020394771534686576731337971640800969336925245078696622140
      Line 77, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 452597849 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 452597849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---