122442b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 3.350s | 3.846ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.370s | 506.078us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 1.740s | 134.469us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 19.890s | 31.260ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.900s | 935.562us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 6.450s | 10.443ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 14.240s | 11.966ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 7.030s | 19.852ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 52.950s | 27.127ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 2.400s | 1.331ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.750s | 171.985us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 3.050s | 764.333us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 2.520s | 413.697us | 0 | 1 | 0.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 2.630s | 581.835us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 3.620s | 1.377ms | 1 | 1 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 2.050s | 135.521us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 2.000s | 1.144ms | 1 | 1 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 2.400s | 1.331ms | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 2.360s | 542.576us | 1 | 1 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.290s | 1.414ms | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 3.050s | 764.333us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 1.930s | 49.973us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.600s | 117.652us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.260s | 104.975us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 36.830s | 5.848ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 17.320s | 562.492us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 1.700s | 68.853us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 17.320s | 562.492us | 1 | 1 | 100.00 |
| rv_dm_csr_rw | 2.260s | 104.975us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 1.830s | 94.262us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 1.560s | 99.764us | 1 | 1 | 100.00 |
| V1 | TOTAL | 25 | 27 | 92.59 | |||
| V2 | idcode | rv_dm_smoke | 3.350s | 3.846ms | 1 | 1 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 2.130s | 296.623us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.950s | 581.876us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.910s | 256.233us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 2.200s | 538.467us | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 26.150s | 13.786ms | 0 | 1 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 1.630s | 163.617us | 0 | 1 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 9.570s | 4.626ms | 1 | 1 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 1.900s | 225.016us | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.760s | 235.716us | 0 | 1 | 0.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 9.020s | 4.267ms | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.740s | 133.288us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.680s | 145.320us | 0 | 1 | 0.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 5.490s | 11.105ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 1.740s | 161.407us | 0 | 1 | 0.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 2.110s | 320.954us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 1.450h | 10.000s | 0 | 1 | 0.00 |
| V2 | alert_test | rv_dm_alert_test | 2.000s | 75.083us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 1.610s | 33.026us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 1.610s | 33.026us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 17.320s | 562.492us | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 2.600s | 117.652us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 2.260s | 104.975us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 6.480s | 1.394ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 17.320s | 562.492us | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 2.600s | 117.652us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 2.260s | 104.975us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 6.480s | 1.394ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 11 | 19 | 57.89 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.430s | 845.532us | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 17.400s | 5.066ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 17.400s | 5.066ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 9.020s | 4.267ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 1.920s | 67.329us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 9.020s | 4.267ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 1.920s | 67.329us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 3.350s | 3.846ms | 1 | 1 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.850s | 361.618us | 1 | 1 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.610s | 58.900us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.610s | 58.900us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.850s | 361.618us | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.770s | 129.951us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 10.102m | 300.000ms | 0 | 1 | 0.00 | |
| TOTAL | 41 | 53 | 77.36 |
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.5918333581595559430064428010633836206080963323909641325951127765469043303748
Line 127, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.57185100367322444822500628848422864555434613584558358606745139475769005289934
Line 127, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test rv_dm_scanmode has 1 failures.
0.rv_dm_scanmode.75984936646219252249157439955946317642046081473355459340711909544380182282232
Line 72, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
0.rv_dm_stress_all.98216300432212960212409653793659930262290043305048261235013278879994587748553
Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:413) [scoreboard] sba_tl_access_q item uncompared: has 1 failures:
0.rv_dm_sba_tl_access.46470834950637429432926278517404443871895652990340574210838282558969606030980
Line 81, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 13786337193 ps: (rv_dm_scoreboard.sv:413) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5440
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6173) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.76485495407679278053020634922120075463688496158527256755271124208180908700217
Line 74, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 161407140 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6173) { a_addr: 'hc11294d0 a_data: 'h6e65c5a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h57 a_opcode: 'h4 a_user: 'h1a355 d_param: 'h0 d_source: 'h57 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 161407140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 1 failures:
0.rv_dm_mem_tl_access_resuming.7992305788952933428408322474704318337256021257068343887702094275040082302060
Line 72, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 413697209 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 413697209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 1 failures:
0.rv_dm_hart_unavail.72626054338340276934311439084004159971089523048082092211076611254844900973277
Line 72, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 145319503 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 145319503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
0.rv_dm_jtag_dmi_debug_disabled.48853292514083887710629127097106216303929826445378153888264593799948243037737
Line 72, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 235716224 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1179883223 [0x465396d7] vs 0 [0x0])
UVM_INFO @ 235716224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5721) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.13044546693141349296023178924549772607836678277755959388554994915463873356982
Line 74, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 129951264 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5721) { a_addr: 'h762385e8 a_data: 'hcaddab47 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6b a_opcode: 'h4 a_user: 'h19344 d_param: 'h0 d_source: 'h6b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 129951264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6027) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.98085487415948139929963162370017478590383046420093411404246208818727950703248
Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 33025990 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6027) { a_addr: 'h9bf6d750 a_data: 'hb03ff56b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h18a82 d_param: 'h0 d_source: 'h21 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 33025990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5663) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.75649355594569812086628374341614824534407614715136447377408200020979244994321
Line 74, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 68853480 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5663) { a_addr: 'ha4bf87cc a_data: 'h1fda7f0c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h76 a_opcode: 'h4 a_user: 'h19fd3 d_param: 'h0 d_source: 'h76 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 68853480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---