RV_TIMER Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.520s	14.764us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.570s	12.106us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.680s	14.713us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.700s	271.204us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.630s	59.376us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.640s	89.370us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.680s	14.713us	1	1	100.00
		rv_timer_csr_aliasing	1.630s	59.376us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.470s	91.432us	1	1	100.00
V2	disabled	rv_timer_disabled	1.770s	580.406us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	6.199m	1.042s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	6.199m	1.042s	1	1	100.00
V2	stress	rv_timer_stress_all	2.510s	3.339ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.770s	37.671us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.530s	78.939us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.480s	226.945us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.480s	226.945us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.570s	12.106us	1	1	100.00
		rv_timer_csr_rw	1.680s	14.713us	1	1	100.00
		rv_timer_csr_aliasing	1.630s	59.376us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	19.859us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.570s	12.106us	1	1	100.00
		rv_timer_csr_rw	1.680s	14.713us	1	1	100.00
		rv_timer_csr_aliasing	1.630s	59.376us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	19.859us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.720s	41.237us	1	1	100.00
		rv_timer_tl_intg_err	2.300s	478.070us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.300s	478.070us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	19.130s	3.289ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.610s	15.198us	1	1	100.00
		rv_timer_max	1.770s	105.377us	1	1	100.00
		TOTAL			19	19	100.00