SPI_DEVICE/1R1W Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	51.450s	15.854ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.820s	56.065us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.240s	95.368us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.860s	549.843us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	13.650s	1.040ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.570s	55.107us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.240s	95.368us	1	1	100.00
		spi_device_csr_aliasing	13.650s	1.040ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.670s	13.581us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.060s	188.065us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.670s	43.563us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.640s	4.046us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.520s	3.850us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.450s	512.771us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.450s	512.771us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.730s	4.058ms	1	1	100.00
		spi_device_tpm_sts_read	1.690s	68.118us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.820s	1.296ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	11.830s	11.282ms	1	1	100.00
		spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.300s	1.749ms	1	1	100.00
		spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.300s	1.749ms	1	1	100.00
		spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.440s	118.941us	1	1	100.00
		spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.440s	118.941us	1	1	100.00
		spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.440s	118.941us	1	1	100.00
		spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.440s	118.941us	1	1	100.00
		spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.440s	118.941us	1	1	100.00
		spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.840s	706.716us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.410s	270.507us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.410s	270.507us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.410s	270.507us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.990s	1.648ms	1	1	100.00
		spi_device_read_buffer_direct	8.770s	1.161ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.410s	270.507us	1	1	100.00
		spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	16.170s	22.159ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.780s	81.377us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.780s	81.377us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	51.450s	15.854ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	26.580s	4.652ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.060m	20.616ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.490s	12.233us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.720s	35.908us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.710s	234.351us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.710s	234.351us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.820s	56.065us	1	1	100.00
		spi_device_csr_rw	3.240s	95.368us	1	1	100.00
		spi_device_csr_aliasing	13.650s	1.040ms	1	1	100.00
		spi_device_same_csr_outstanding	4.220s	326.783us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.820s	56.065us	1	1	100.00
		spi_device_csr_rw	3.240s	95.368us	1	1	100.00
		spi_device_csr_aliasing	13.650s	1.040ms	1	1	100.00
		spi_device_same_csr_outstanding	4.220s	326.783us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.900s	46.526us	1	1	100.00
		spi_device_tl_intg_err	10.480s	840.022us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.480s	840.022us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.540s	112.148us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.80621489849935767545167796867746948499688638469074007544936981077067763664992
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3006384 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[14])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3006384 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3006384 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[910])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.84662225494103581443491485964488100269312920773238137909585093594910739559408
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1433156 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6d1200 [11011010001001000000000] vs 0x0 [0])
        UVM_ERROR @   1503156 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x673081 [11001110011000010000001] vs 0x0 [0])
        UVM_ERROR @   1515156 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xce0900 [110011100000100100000000] vs 0x0 [0])
        UVM_ERROR @   1529156 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x559875 [10101011001100001110101] vs 0x0 [0])
        UVM_ERROR @   1569156 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5551e7 [10101010101000111100111] vs 0x0 [0])