SPI_HOST Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	17.000s	481.625us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	21.545us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	29.310us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	746.024us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	34.300us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	33.387us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	29.310us	1	1	100.00
		spi_host_csr_aliasing	4.000s	34.300us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	33.579us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	21.823us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	8.000s	41.172us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	7.000s	73.290us	1	1	100.00
		spi_host_error_cmd	5.000s	49.976us	1	1	100.00
		spi_host_event	15.000s	1.199ms	1	1	100.00
V2	clock_rate	spi_host_speed	10.000s	192.069us	1	1	100.00
V2	speed	spi_host_speed	10.000s	192.069us	1	1	100.00
V2	chip_select_timing	spi_host_speed	10.000s	192.069us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	10.000s	75.847us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	145.244us	1	1	100.00
V2	cpol_cpha	spi_host_speed	10.000s	192.069us	1	1	100.00
V2	full_cycle	spi_host_speed	10.000s	192.069us	1	1	100.00
V2	duplex	spi_host_smoke	17.000s	481.625us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	17.000s	481.625us	1	1	100.00
V2	stress_all	spi_host_stress_all	16.000s	453.479us	1	1	100.00
V2	spien	spi_host_spien	6.000s	548.035us	1	1	100.00
V2	stall	spi_host_status_stall	24.000s	1.129ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	120.933us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	7.000s	73.290us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	40.932us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	45.146us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	80.975us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	80.975us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	21.545us	1	1	100.00
		spi_host_csr_rw	4.000s	29.310us	1	1	100.00
		spi_host_csr_aliasing	4.000s	34.300us	1	1	100.00
		spi_host_same_csr_outstanding	5.000s	16.323us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	21.545us	1	1	100.00
		spi_host_csr_rw	4.000s	29.310us	1	1	100.00
		spi_host_csr_aliasing	4.000s	34.300us	1	1	100.00
		spi_host_same_csr_outstanding	5.000s	16.323us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	387.043us	1	1	100.00
		spi_host_sec_cm	4.000s	148.812us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	387.043us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.833m	5.794ms	1	1	100.00
		TOTAL			26	26	100.00