SRAM_CTRL/MAIN Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	52.310s	454.059us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.650s	19.941us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.570s	11.741us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.300s	44.774us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.670s	21.002us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.720s	1.554ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.570s	11.741us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	21.002us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.863m	14.135ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.041m	12.279ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	11.622m	20.847ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.067m	3.511ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	32.285m	130.755ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.940m	67.693ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	36.920s	37.644ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.577m	15.501ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.640s	3.117ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.226m	158.154ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	11.780s	2.605ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	23.970s	779.024us	1	1	100.00
		sram_ctrl_throughput_w_readback	44.430s	1.858ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.138m	3.729ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.260s	621.502us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	31.659m	38.433ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.430s	27.170us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.160s	24.662us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.160s	24.662us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.650s	19.941us	1	1	100.00
		sram_ctrl_csr_rw	1.570s	11.741us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	21.002us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.640s	33.837us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.650s	19.941us	1	1	100.00
		sram_ctrl_csr_rw	1.570s	11.741us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	21.002us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.640s	33.837us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	35.870s	70.441ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.620s	6.790us	0	1	0.00
		sram_ctrl_tl_intg_err	2.740s	180.198us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.620s	6.790us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.740s	180.198us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.138m	3.729ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.138m	3.729ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.570s	11.741us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.577m	15.501ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.577m	15.501ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.577m	15.501ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	36.920s	37.644ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.740s	679.712us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	35.870s	70.441ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.050s	1.375ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	52.310s	454.059us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	52.310s	454.059us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.577m	15.501ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.620s	6.790us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	36.920s	37.644ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.620s	6.790us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.620s	6.790us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	52.310s	454.059us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.620s	6.790us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.875m	4.739ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.113035948706978670531741873524400893024716737817761848162854047596825759170434
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 679712099 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 679712099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.59193885450857264673314485181976390767778198876916359482595212123660863919940
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   6790491 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   6790491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---