SRAM_CTRL/RET Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.720s	149.356us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.930s	60.918us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.050s	41.873us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.640s	543.995us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.770s	25.334us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.100s	76.195us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.050s	41.873us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	25.334us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.050s	1.999ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.470s	118.044us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	13.734m	4.059ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.713m	2.286ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	44.170s	10.583ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.868m	2.376ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.210s	1.983ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.593m	7.893ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	2.070s	77.688us	1	1	100.00
		sram_ctrl_partial_access_b2b	1.573m	3.606ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	14.070s	219.199us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.180s	237.859us	1	1	100.00
		sram_ctrl_throughput_w_readback	39.130s	255.050us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.829m	12.407ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.170s	86.674us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	33.812m	38.304ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	2.070s	56.048us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.100s	90.391us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.100s	90.391us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.930s	60.918us	1	1	100.00
		sram_ctrl_csr_rw	2.050s	41.873us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	25.334us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.180s	55.519us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.930s	60.918us	1	1	100.00
		sram_ctrl_csr_rw	2.050s	41.873us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	25.334us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.180s	55.519us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.410s	259.880us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.500s	1.588us	0	1	0.00
		sram_ctrl_tl_intg_err	2.970s	201.760us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.500s	1.588us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.970s	201.760us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.829m	12.407ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.829m	12.407ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.050s	41.873us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.593m	7.893ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.593m	7.893ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.593m	7.893ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.210s	1.983ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.060s	42.478us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.410s	259.880us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.790s	33.498us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.720s	149.356us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.720s	149.356us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.593m	7.893ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.500s	1.588us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.210s	1.983ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.500s	1.588us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.500s	1.588us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.720s	149.356us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.500s	1.588us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.476m	1.883ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.12345391815203067565798498691542526805092495987235956372762870964751653729154
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1588430 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1588430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---