UART Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: 122442b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	13.640s	5.724ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.760s	1.104ms	1	1	100.00
V1	csr_rw	uart_csr_rw	1.620s	41.087us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.120s	251.591us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.710s	18.389us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.720s	22.346us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.620s	41.087us	1	1	100.00
		uart_csr_aliasing	1.710s	18.389us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	51.920s	115.175ms	1	1	100.00
V2	parity	uart_smoke	13.640s	5.724ms	1	1	100.00
		uart_tx_rx	51.920s	115.175ms	1	1	100.00
V2	parity_error	uart_intr	21.020s	23.020ms	1	1	100.00
		uart_rx_parity_err	10.620s	49.460ms	1	1	100.00
V2	watermark	uart_tx_rx	51.920s	115.175ms	1	1	100.00
		uart_intr	21.020s	23.020ms	1	1	100.00
V2	fifo_full	uart_fifo_full	49.720s	88.129ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	31.160s	130.191ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	57.020s	70.140ms	1	1	100.00
V2	rx_frame_err	uart_intr	21.020s	23.020ms	1	1	100.00
V2	rx_break_err	uart_intr	21.020s	23.020ms	1	1	100.00
V2	rx_timeout	uart_intr	21.020s	23.020ms	1	1	100.00
V2	perf	uart_perf	12.484m	20.689ms	1	1	100.00
V2	sys_loopback	uart_loopback	8.250s	6.331ms	1	1	100.00
V2	line_loopback	uart_loopback	8.250s	6.331ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	31.990s	105.472ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	7.980s	7.083ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.020s	857.575us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	12.900s	2.631ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	12.607m	124.807ms	1	1	100.00
V2	stress_all	uart_stress_all	4.487m	142.555ms	1	1	100.00
V2	alert_test	uart_alert_test	1.480s	34.261us	1	1	100.00
V2	intr_test	uart_intr_test	1.620s	13.875us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.920s	42.519us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.920s	42.519us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.760s	1.104ms	1	1	100.00
		uart_csr_rw	1.620s	41.087us	1	1	100.00
		uart_csr_aliasing	1.710s	18.389us	1	1	100.00
		uart_same_csr_outstanding	1.730s	16.620us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.760s	1.104ms	1	1	100.00
		uart_csr_rw	1.620s	41.087us	1	1	100.00
		uart_csr_aliasing	1.710s	18.389us	1	1	100.00
		uart_same_csr_outstanding	1.730s	16.620us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.710s	39.807us	1	1	100.00
		uart_tl_intg_err	1.900s	432.766us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.900s	432.766us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	23.170s	3.896ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00