CHIP Simulation Results

Thursday May 08 2025 17:04:53 UTC

GitHub Revision: `122442b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.825m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.825m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	12.274s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	12.463s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.092s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.999m	4.765ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.999m	4.765ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.999m	4.765ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	42.350s	10.300us	0	1	0.00
		chip_sw_example_manufacturer	2.580m		0	1	0.00
		chip_sw_example_concurrency	4.679m	4.880ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.485s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.170s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	11.590s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	11.590s		0	1	0.00
V1	xbar_smoke	xbar_smoke	12.130s	12.628us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.726m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.048m	8.008ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.077m	4.296ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	11.502s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.271s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.290s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.949s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.630s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.630s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.088m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.079m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.317m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.317m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.939m	5.592ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.600m	3.754ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.938m	14.992ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.946s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.991s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	15.875m	29.562ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.851m	4.696ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.322m	18.026ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.322m	18.026ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.406s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.613m	4.493ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.613m	4.493ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.007m	18.015ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.996m	4.014ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.471m	3.930ms	1	1	100.00
		chip_sw_aes_idle	4.713m	4.851ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.554m	3.200ms	1	1	100.00
		chip_sw_kmac_idle	3.850m	5.076ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.389m	12.008ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	11.349m	12.020ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.726m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.374m	12.022ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.402s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.798s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.353s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.471s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.903s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.665s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.917s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.402s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.798s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.353s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.471s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.903s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.665s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.917s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.834s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.960s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.090s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.920s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.730s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.525s		0	1	0.00
		chip_sw_clkmgr_jitter	3.675m	5.504ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.260m	4.669ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.989s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	47.580s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	54.430s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.048m	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	58.330s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	49.530s	10.360us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.646s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.150s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.943s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.730s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.336m	14.594ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.548m	16.265ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.613m	4.493ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.931s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.548m	16.265ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	13.080s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13.869s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.089s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	18.162s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	10.796s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.336m	14.594ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.938m	14.992ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.460m	20.020ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.043m	5.573ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.148m	10.031ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.160m	4.853ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.336m	14.594ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	16.471s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.072s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.336m	14.594ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.465s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.148m	10.031ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.787s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.385s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.377s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.645s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.632s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.599s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.072s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	14.071s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.896s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	14.071s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	14.071s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	14.071s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.655m	6.436ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.415s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.629s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.520s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.831s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.071s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.873m	8.083ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.121m	11.298ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.228s		0	1	0.00
		chip_prim_tl_access	12.879m	13.912ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.402s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.798s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.353s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.471s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.903s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.665s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.917s		0	1	0.00
		chip_rv_dm_lc_disabled	15.875m	29.562ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.611m	4.967ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	46.960s	10.400us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.485m	4.212ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.713m	4.851ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.762m	3.389ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	48.090s	10.380us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.554m	3.200ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.882m	5.586ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.481m	4.660ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	52.730s	10.260us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.873m	8.083ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	14.071s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	43.880s	10.280us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.621m	4.133ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.850m	5.076ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.937s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.937s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.483s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.430m	5.463ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.353s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.873m	8.083ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.920s	10.160us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.521s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.834s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.471m	3.930ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.471m	3.930ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.471m	3.930ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.322m	6.919ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.121m	11.298ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.121m	11.298ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.000m	9.561ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.525s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.228s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.336m	14.594ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.317m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	14.071s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.322m	6.919ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.873m	8.083ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.000m	9.561ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.109m	3.270ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.322m	6.919ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.873m	8.083ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.000m	9.561ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.109m	3.270ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	14.071s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.270s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.896s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.415s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.629s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.520s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.831s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.071s		0	1	0.00
		chip_prim_tl_access	12.879m	13.912ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	12.879m	13.912ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.192s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.167s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.150s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.834s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.960s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.090s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.920s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.730s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.525s		0	1	0.00
		chip_sw_clkmgr_jitter	3.675m	5.504ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.610m	5.913ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.610m	5.913ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.931m	5.032ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.707m	3.758ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.580m	4.540ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.268m	5.470ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.494m	5.263ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.395m	3.561ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.109m	3.270ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.460m	20.020ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.460m	20.020ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.206m	5.304ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.803m	5.584ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.274m	4.240ms	1	1	100.00
		chip_sw_csrng_smoketest	3.279m	4.352ms	1	1	100.00
		chip_sw_gpio_smoketest	4.307m	6.055ms	1	1	100.00
		chip_sw_hmac_smoketest	4.700m	5.131ms	1	1	100.00
		chip_sw_kmac_smoketest	4.999m	5.925ms	1	1	100.00
		chip_sw_otbn_smoketest	5.472m	6.114ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.506m	5.868ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.092m	4.995ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.013m	5.115ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.088m	4.208ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.511m	4.409ms	1	1	100.00
		chip_sw_uart_smoketest	3.538m	4.008ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.248s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.485s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.726m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.953s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.393m	4.361ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.053m	5.566ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.508m	6.553ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.776m	4.721ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	10.905s		0	1	0.00
		chip_rv_dm_lc_disabled	15.875m	29.562ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	17.766s		0	1	0.00
		chip_sw_lc_walkthrough_prod	16.199s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.025s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.035s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	10.905s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.474s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	10.857s		0	1	0.00
		rom_volatile_raw_unlock	11.259s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	16.776s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.185m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.388m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.850m	5.250ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.850m	5.250ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	11.590s		0	1	0.00
		chip_same_csr_outstanding	10.240s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	11.590s		0	1	0.00
		chip_same_csr_outstanding	10.240s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	58.380s	125.360us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.890s	13.318us	1	1	100.00
		xbar_smoke_large_delays	4.697m	2.506ms	1	1	100.00
		xbar_smoke_slow_rsp	5.480m	1.981ms	1	1	100.00
		xbar_random_zero_delays	1.079m	55.488us	1	1	100.00
		xbar_random_large_delays	5.028m	2.582ms	1	1	100.00
		xbar_random_slow_rsp	30.714m	11.678ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	47.220s	97.271us	1	1	100.00
		xbar_error_and_unmapped_addr	15.860s	20.898us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.272m	205.892us	1	1	100.00
		xbar_error_and_unmapped_addr	15.860s	20.898us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.644m	587.723us	1	1	100.00
		xbar_access_same_device_slow_rsp	17.771m	6.379ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	9.850s	10.259us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	8.011m	1.207ms	1	1	100.00
		xbar_stress_all_with_error	9.803m	1.635ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	17.079m	557.789us	1	1	100.00
		xbar_stress_all_with_reset_error	1.593m	49.881us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.351s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.987s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	14.574s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.833s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.444s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.586s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.762s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.104s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.654s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.077s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.796s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.909s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.253s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.466s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.438s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.607s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.976s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.636s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.138s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.065s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.243s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.756s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.915s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.392s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.068s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.135s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.985s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.307s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.968s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.015s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.905s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.444s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.679s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.336s		0	1	0.00
		rom_e2e_asm_init_dev	12.088s		0	1	0.00
		rom_e2e_asm_init_prod	11.127s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.228s		0	1	0.00
		rom_e2e_asm_init_rma	12.349s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.702s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.650s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.472s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.326s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.446m	4.418ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.014m	3.728ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.505s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.370s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.351s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	15.333s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.336m	14.594ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.750s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.664m	12.622ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.257s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.902s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.505s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.370s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.351s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.372s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.251s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.764s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	41.742s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.483m	14.044ms	1	1	100.00
		chip_plic_all_irqs_0	9.990m	5.170ms	1	1	100.00
		chip_plic_all_irqs_10	10.899m	7.613ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.753m	5.589ms	1	1	100.00
		chip_sw_dma_abort	4.185m	4.761ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.372s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.327s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.664s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.069s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.900s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.024s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.411s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.273s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.713s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.979s		0	1	0.00
		chip_sw_mbx_smoketest	4.074m	4.221ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.89758922519584064989629512124226671254050227675485558851358278059354525052537
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (6a2a47)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 144.230s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.55836212584870786195877143915122047475322416837031148355597788773188440553022
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (a56690)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 128.833s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.45841943509189050951147060369892773053792240651028302138390735829920413052338
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (13a517)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 114.204s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.9282356731081670320597300047394762571702708686470602499943683191120823318230
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (ff9182)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 114.182s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.24470100813106717190062001063586784140526118949182415271163103446308757323691
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (9ca34d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 99.678s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.36494814128589357034201353652528841153619379378854523865591059475495966742144
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.33544483847616861624017643108425466932031765663951381105635466394213657980157
    Line 413, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.71151510588531399753794071327132337950320909094175658950512273534869808149135
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.56132889340723091601317255075674112447702357774336614935018194296230595040531
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.90165242645319154266972402179894433611793880775130958633476732002175377999150
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.60102116949022975176976998610348156715576646491048064422743933759105994333959
Line 461, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20019.836395 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20019.836395 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.10505015163655876316064459337478709681777115510570248781168354068625637967680
Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.117174 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.117174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.18903546365702476391929820704831959333265675859894252682488572521439852174454
Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18014.773567 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18014.773567 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.37990533704322019546030004290898994583761144146231396830390239523558489880717
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12020.454628 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12020.454628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.18475566595927953122212404909955339240177310271594569839412464728187101504141
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.75163440839878269633999680873428237432394637661183468853657758036900405715274
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.17946280083132288703042158881581854446534110585787993202530685341351166544977
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.2399652063122710221250218772049290153458562955962459762315427509283282961444
Line 469, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8082.906840 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (35942144021788907388314616503389318773621585226126216579308859937806939349472 [0x4f768858bec08b14af0dddb3d16da8b24e4e2c7d0f0c6218d2ca6efd87bc61e0] vs 55230852516449744606301837942256183388880198542620791484409138937090516547025 [0x7a1b8e029e044082d62752c7f8d6e3f7482be16c98406ac1182dcc1962a175d1])
  UVM_INFO @ 8082.906840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.48826418398950873457459349961601626152349413737090715180426427409932427549124
Line 461, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6436.289240 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (13775921466283694848669939734088903496912444228521347679921289907114339567076 [0x1e74e52e575d0d66194fed28d96851d60a5fbcca688b31857e5432291c3585e4] vs 37916945172169774138104696782309157616695684570363176866375861916283411479281 [0x53d43afe7a9918426a1aa2e9bb6fb3388eaa7bc7be495cda450a3d467f99baf1])
  UVM_INFO @ 6436.289240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.72060414702325401182147137783138379034214852531299283461301776975804948118313
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.086042 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.086042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_otbn_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_otbn_trans.44712650342886631210323128522020558082195062148701011438344506787321788385613
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log
```
  UVM_ERROR @ 12022.242297 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.242297 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.54560576394509022815060355584255546540101691802239754936503508273965521471883
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5591.730892 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hd570c23d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h1  a_user: 'h24887  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5591.730892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.90268764306807493352147356746089861350604938021848399697167025252867666352955
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3753.954779 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h927b9d8e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6  a_opcode: 'h1  a_user: 'h248b2  d_param: 'h0  d_source: 'h6  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3753.954779 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.98442930973119391717918674768817867693355753510754405935888978949158413679579
    Line 615, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.38787868071687089552040017621643464754778036576607300947024707988078188332039
    Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4295.581106 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4295.581106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.105446664735698653969705463788151618841019977705799582100143225922361465787797
    Line 665, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10030.969660 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10030.969660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.10222358240511824425144019120589356979608517549074902051363085215399471560297
    Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5032.062450 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5032.062450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.114050519382588988785089055826370250790488643161563812486094890839840738731202
    Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3757.631816 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3757.631816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.10735104860272154611271820459997896623678183774114709837959363923963101224653
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4492.868256 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4492.868256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.65241664001047013526492198627759895646971841748302085141522256393822608696101
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5470.465020 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5470.465020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.38704237348898505309404347832440051678110746844240039044584871799552719420588
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.7124138652438603630924739548168401946796021070643300390954861859564049664531
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5250.080808 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5250.080808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.21621035340559063147985312569574940326701472479179055866635616308686701629668
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14992.229732 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14992.229732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.113818535100737639225066434621185836584950779646076733453172606682250749000517
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.5033549958647942981744837655539928120933395748042866067715114961004163690474
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4760.976626 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4760.976626 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```