DMA Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	342.756us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	283.507us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	399.508us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	156.608us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	39.627us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	923.202us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	886.426us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	51.404us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	39.627us	1	1	100.00
		dma_csr_aliasing	7.000s	886.426us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	19.000s	5.114ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	49.433m	345.490ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	34.917m	218.756ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	3.850m	22.035ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	49.433m	345.490ms	1	1	100.00
V2	dma_abort	dma_abort	11.000s	827.608us	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.967m	53.595ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	30.428us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	322.765us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	322.765us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	156.608us	1	1	100.00
		dma_csr_rw	4.000s	39.627us	1	1	100.00
		dma_csr_aliasing	7.000s	886.426us	1	1	100.00
		dma_same_csr_outstanding	5.000s	111.995us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	156.608us	1	1	100.00
		dma_csr_rw	4.000s	39.627us	1	1	100.00
		dma_csr_aliasing	7.000s	886.426us	1	1	100.00
		dma_same_csr_outstanding	5.000s	111.995us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	25.000s	761.466us	1	1	100.00
		dma_generic_stress	3.850m	22.035ms	1	1	100.00
		dma_handshake_stress	49.433m	345.490ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	405.888us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	58.000s	13.481ms	1	1	100.00
		dma_longer_transfer	5.000s	1.342ms	1	1	100.00
		TOTAL			21	21	100.00