EDN Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.680s	20.129us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.730s	26.596us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.650s	25.576us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.350s	131.670us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.090s	90.553us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.220s	28.646us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.650s	25.576us	1	1	100.00
		edn_csr_aliasing	2.090s	90.553us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.800s	41.279us	1	1	100.00
V2	csrng_commands	edn_genbits	1.800s	41.279us	1	1	100.00
V2	genbits	edn_genbits	1.800s	41.279us	1	1	100.00
V2	interrupts	edn_intr	1.760s	26.467us	1	1	100.00
V2	alerts	edn_alert	1.730s	63.678us	1	1	100.00
V2	errs	edn_err	1.600s	28.033us	1	1	100.00
V2	disable	edn_disable	1.730s	43.944us	1	1	100.00
		edn_disable_auto_req_mode	2.070s	40.641us	1	1	100.00
V2	stress_all	edn_stress_all	4.240s	634.063us	1	1	100.00
V2	intr_test	edn_intr_test	1.830s	73.616us	1	1	100.00
V2	alert_test	edn_alert_test	1.830s	47.879us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.320s	86.789us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.320s	86.789us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.730s	26.596us	1	1	100.00
		edn_csr_rw	1.650s	25.576us	1	1	100.00
		edn_csr_aliasing	2.090s	90.553us	1	1	100.00
		edn_same_csr_outstanding	1.670s	43.467us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.730s	26.596us	1	1	100.00
		edn_csr_rw	1.650s	25.576us	1	1	100.00
		edn_csr_aliasing	2.090s	90.553us	1	1	100.00
		edn_same_csr_outstanding	1.670s	43.467us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.300s	1.749ms	1	1	100.00
		edn_tl_intg_err	2.870s	92.987us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.740s	44.423us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.730s	63.678us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.300s	1.749ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.300s	1.749ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.300s	1.749ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.300s	1.749ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.730s	63.678us	1	1	100.00
		edn_sec_cm	4.300s	1.749ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.730s	63.678us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.870s	92.987us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.333m	10.155ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00