HMAC Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.490s 133.840us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 2.010s 209.084us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.690s 36.908us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.570s 743.098us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.580s 301.252us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.550s 291.257us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.690s 36.908us 1 1 100.00
hmac_csr_aliasing 6.580s 301.252us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 54.270s 5.653ms 1 1 100.00
V2 back_pressure hmac_back_pressure 50.430s 1.573ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.490s 1.782ms 1 1 100.00
hmac_test_sha384_vectors 5.779m 11.693ms 1 1 100.00
hmac_test_sha512_vectors 6.555m 11.391ms 1 1 100.00
hmac_test_hmac256_vectors 14.240s 1.191ms 1 1 100.00
hmac_test_hmac384_vectors 8.260s 1.898ms 1 1 100.00
hmac_test_hmac512_vectors 12.550s 711.404us 1 1 100.00
V2 burst_wr hmac_burst_wr 8.710s 798.256us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.107m 8.675ms 1 1 100.00
V2 error hmac_error 1.099m 102.409ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.251m 10.516ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.490s 133.840us 1 1 100.00
hmac_long_msg 54.270s 5.653ms 1 1 100.00
hmac_back_pressure 50.430s 1.573ms 1 1 100.00
hmac_datapath_stress 4.107m 8.675ms 1 1 100.00
hmac_burst_wr 8.710s 798.256us 1 1 100.00
hmac_stress_all 3.780s 260.194us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.490s 133.840us 1 1 100.00
hmac_long_msg 54.270s 5.653ms 1 1 100.00
hmac_back_pressure 50.430s 1.573ms 1 1 100.00
hmac_datapath_stress 4.107m 8.675ms 1 1 100.00
hmac_wipe_secret 1.251m 10.516ms 1 1 100.00
hmac_test_sha256_vectors 8.490s 1.782ms 1 1 100.00
hmac_test_sha384_vectors 5.779m 11.693ms 1 1 100.00
hmac_test_sha512_vectors 6.555m 11.391ms 1 1 100.00
hmac_test_hmac256_vectors 14.240s 1.191ms 1 1 100.00
hmac_test_hmac384_vectors 8.260s 1.898ms 1 1 100.00
hmac_test_hmac512_vectors 12.550s 711.404us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.490s 133.840us 1 1 100.00
hmac_long_msg 54.270s 5.653ms 1 1 100.00
hmac_back_pressure 50.430s 1.573ms 1 1 100.00
hmac_datapath_stress 4.107m 8.675ms 1 1 100.00
hmac_burst_wr 8.710s 798.256us 1 1 100.00
hmac_error 1.099m 102.409ms 1 1 100.00
hmac_wipe_secret 1.251m 10.516ms 1 1 100.00
hmac_test_sha256_vectors 8.490s 1.782ms 1 1 100.00
hmac_test_sha384_vectors 5.779m 11.693ms 1 1 100.00
hmac_test_sha512_vectors 6.555m 11.391ms 1 1 100.00
hmac_test_hmac256_vectors 14.240s 1.191ms 1 1 100.00
hmac_test_hmac384_vectors 8.260s 1.898ms 1 1 100.00
hmac_test_hmac512_vectors 12.550s 711.404us 1 1 100.00
hmac_stress_all 3.780s 260.194us 1 1 100.00
V2 stress_all hmac_stress_all 3.780s 260.194us 1 1 100.00
V2 alert_test hmac_alert_test 1.460s 27.206us 1 1 100.00
V2 intr_test hmac_intr_test 1.710s 19.718us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.500s 122.172us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.500s 122.172us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 2.010s 209.084us 1 1 100.00
hmac_csr_rw 1.690s 36.908us 1 1 100.00
hmac_csr_aliasing 6.580s 301.252us 1 1 100.00
hmac_same_csr_outstanding 2.300s 219.187us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 2.010s 209.084us 1 1 100.00
hmac_csr_rw 1.690s 36.908us 1 1 100.00
hmac_csr_aliasing 6.580s 301.252us 1 1 100.00
hmac_same_csr_outstanding 2.300s 219.187us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.910s 90.537us 1 1 100.00
hmac_tl_intg_err 2.490s 166.433us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.490s 166.433us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.490s 133.840us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.590s 659.153us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.657m 11.053ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.900s 29.572us 1 1 100.00
TOTAL 28 28 100.00