I2C Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	23.140s	31.395ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.960s	1.388ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.670s	52.040us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.780s	54.815us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.900s	465.416us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.900s	62.060us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.070s	65.757us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.780s	54.815us	1	1	100.00
		i2c_csr_aliasing	1.900s	62.060us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.050s	1.609ms	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	5.602m	9.021ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	8.250s	2.688ms	1	1	100.00
V2	host_override	i2c_host_override	1.700s	45.626us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	59.880s	3.213ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.425m	7.441ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.760s	1.015ms	1	1	100.00
		i2c_host_fifo_fmt_empty	5.240s	526.370us	1	1	100.00
		i2c_host_fifo_reset_rx	8.080s	681.550us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	41.360s	7.930ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.390s	1.247ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.420s	252.379us	1	1	100.00
V2	target_glitch	i2c_target_glitch	9.130s	15.579ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	3.150m	31.012ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.240s	2.544ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	9.680s	2.247ms	1	1	100.00
		i2c_target_intr_smoke	4.340s	3.022ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.770s	357.604us	1	1	100.00
		i2c_target_fifo_reset_tx	1.720s	167.680us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	7.180m	68.012ms	1	1	100.00
		i2c_target_stress_rd	9.680s	2.247ms	1	1	100.00
		i2c_target_intr_stress_wr	4.272m	24.930ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.250s	2.710ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.150s	3.440ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.870s	1.969ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.400s	1.050ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.470s	1.586ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	3.100s	167.792us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	8.250s	2.688ms	1	1	100.00
		i2c_host_perf_precise	3.720s	267.036us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.390s	1.247ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.660s	100.722us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.750s	2.102ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.690s	444.848us	1	1	100.00
		i2c_target_nack_txstretch	2.180s	615.452us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	18.140s	2.494ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.800s	450.595us	1	1	100.00
V2	alert_test	i2c_alert_test	1.560s	17.034us	1	1	100.00
V2	intr_test	i2c_intr_test	1.710s	14.654us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.560s	128.576us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.560s	128.576us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.670s	52.040us	1	1	100.00
		i2c_csr_rw	1.780s	54.815us	1	1	100.00
		i2c_csr_aliasing	1.900s	62.060us	1	1	100.00
		i2c_same_csr_outstanding	1.980s	236.317us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.670s	52.040us	1	1	100.00
		i2c_csr_rw	1.780s	54.815us	1	1	100.00
		i2c_csr_aliasing	1.900s	62.060us	1	1	100.00
		i2c_same_csr_outstanding	1.980s	236.317us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.590s	330.669us	1	1	100.00
		i2c_sec_cm	1.820s	86.992us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.590s	330.669us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	12.400s	960.847us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.580s	36.405us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	3.387m	600.000ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.31321887524281899746288552729324467930560594155659266485702261830598943584862
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  36405081 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @  36405081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.6774887869108673590734099694777796452193390290291829500631131533447545535062
      Line 86, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 960847293 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 960847293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.48408785232294400729440667242690781169898506340772885138481031442624749822017
      Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.41152713158515022663413714582363175041609926092622766683663026349137144753345
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 615451740 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 615451740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---