KEYMGR Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	9.740s	2.326ms	1	1	100.00
V1	random	keymgr_random	3.970s	929.274us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.630s	44.886us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.720s	42.558us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.320s	1.815ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.970s	67.629us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.680s	51.684us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.720s	42.558us	1	1	100.00
		keymgr_csr_aliasing	3.970s	67.629us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.470s	194.344us	1	1	100.00
V2	sideload	keymgr_sideload	2.920s	209.258us	1	1	100.00
		keymgr_sideload_kmac	2.490s	26.431us	1	1	100.00
		keymgr_sideload_aes	2.860s	113.689us	1	1	100.00
		keymgr_sideload_otbn	3.760s	385.988us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.430s	61.482us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.650s	209.502us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.750s	57.853us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.640s	122.801us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	5.470s	1.651ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	4.920s	596.355us	1	1	100.00
V2	stress_all	keymgr_stress_all	21.720s	1.626ms	0	1	0.00
V2	intr_test	keymgr_intr_test	1.550s	18.173us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.500s	30.025us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.070s	114.446us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.070s	114.446us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.630s	44.886us	1	1	100.00
		keymgr_csr_rw	1.720s	42.558us	1	1	100.00
		keymgr_csr_aliasing	3.970s	67.629us	1	1	100.00
		keymgr_same_csr_outstanding	1.940s	68.602us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.630s	44.886us	1	1	100.00
		keymgr_csr_rw	1.720s	42.558us	1	1	100.00
		keymgr_csr_aliasing	3.970s	67.629us	1	1	100.00
		keymgr_same_csr_outstanding	1.940s	68.602us	0	1	0.00
V2		TOTAL			14	16	87.50
V2S	sec_cm_additional_check	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
		keymgr_tl_intg_err	4.450s	136.494us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.330s	717.460us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.330s	717.460us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.330s	717.460us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.330s	717.460us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.150s	120.616us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.450s	136.494us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.330s	717.460us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.470s	194.344us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.970s	929.274us	1	1	100.00
		keymgr_csr_rw	1.720s	42.558us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.970s	929.274us	1	1	100.00
		keymgr_csr_rw	1.720s	42.558us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.970s	929.274us	1	1	100.00
		keymgr_csr_rw	1.720s	42.558us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.650s	209.502us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	5.470s	1.651ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	5.470s	1.651ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.970s	929.274us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.960s	376.357us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.520s	334.300us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.650s	209.502us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.520s	334.300us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.520s	334.300us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.520s	334.300us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.110s	883.617us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.520s	334.300us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.610s	403.296us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 0.keymgr_stress_all.94179367465261888728489241521945424904126631712130638809760920659731418329755
      Line 3115, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 1626277216 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (492458675 [0x1d5a52b3] vs 492458675 [0x1d5a52b3]) reg name: keymgr_reg_block.sw_share1_output_3
        UVM_INFO @ 1626277216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.37158706418632029542195815011733063980588101537331271078724972629686067682470
      Line 1796, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 403296182 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 403296182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.30485599919947364200337102231001732821259744342883340943809087011277794213364
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @  68601698 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @  68601698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---