KMAC/MASKED Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	46.180s	1.983ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.070s	34.303us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.820s	24.628us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.180s	971.236us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.890s	967.857us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	31.430us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.820s	24.628us	1	1	100.00
		kmac_csr_aliasing	7.890s	967.857us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.720s	13.375us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.270s	20.620us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	22.636m	38.463ms	1	1	100.00
V2	burst_write	kmac_burst_write	11.453m	26.586ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	45.670s	10.963ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.618m	61.394ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.915m	13.362ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.370s	590.386us	1	1	100.00
		kmac_test_vectors_shake_128	2.789m	33.441ms	1	1	100.00
		kmac_test_vectors_shake_256	4.996m	30.688ms	1	1	100.00
		kmac_test_vectors_kmac	4.500s	176.396us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.740s	48.979us	1	1	100.00
V2	sideload	kmac_sideload	5.225m	6.671ms	1	1	100.00
V2	app	kmac_app	26.970s	1.196ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.119m	4.808ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.305m	28.467ms	1	1	100.00
V2	error	kmac_error	2.086m	7.793ms	1	1	100.00
V2	key_error	kmac_key_error	5.370s	8.323ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.690s	670.487us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.750s	4.343ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.960s	38.334us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	15.250s	3.009ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	18.970s	533.573us	1	1	100.00
V2	stress_all	kmac_stress_all	19.257m	18.252ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.810s	16.149us	1	1	100.00
V2	alert_test	kmac_alert_test	1.900s	208.466us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.120s	194.050us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.120s	194.050us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.070s	34.303us	1	1	100.00
		kmac_csr_rw	1.820s	24.628us	1	1	100.00
		kmac_csr_aliasing	7.890s	967.857us	1	1	100.00
		kmac_same_csr_outstanding	2.940s	440.903us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.070s	34.303us	1	1	100.00
		kmac_csr_rw	1.820s	24.628us	1	1	100.00
		kmac_csr_aliasing	7.890s	967.857us	1	1	100.00
		kmac_same_csr_outstanding	2.940s	440.903us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.830s	236.004us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.830s	236.004us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.830s	236.004us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.830s	236.004us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.310s	634.253us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	24.680s	9.690ms	1	1	100.00
		kmac_tl_intg_err	4.280s	283.252us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.280s	283.252us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	18.970s	533.573us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	46.180s	1.983ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.225m	6.671ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.830s	236.004us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	24.680s	9.690ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	24.680s	9.690ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	24.680s	9.690ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	46.180s	1.983ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	18.970s	533.573us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	24.680s	9.690ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.084m	8.053ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	46.180s	1.983ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.202m	7.188ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.34532374854846935050543588021538414237892772940310405153833913150501156832575
      Line 160, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7188134622 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7188134622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---