KMAC/UNMASKED Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	13.980s	501.265us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.670s	27.285us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.670s	68.364us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.440s	6.845ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.740s	257.048us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.810s	345.308us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.670s	68.364us	1	1	100.00
		kmac_csr_aliasing	3.740s	257.048us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.450s	85.521us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.860s	35.342us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	12.104m	78.905ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.223m	65.454ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	17.562m	17.455ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.620s	2.112ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.430s	1.669ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.890s	518.447us	1	1	100.00
		kmac_test_vectors_shake_128	1.590m	9.023ms	1	1	100.00
		kmac_test_vectors_shake_256	17.029m	17.122ms	1	1	100.00
		kmac_test_vectors_kmac	2.620s	37.629us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.280s	29.411us	1	1	100.00
V2	sideload	kmac_sideload	3.055m	12.388ms	1	1	100.00
V2	app	kmac_app	2.683m	51.770ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.372m	4.725ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.590m	7.388ms	1	1	100.00
V2	error	kmac_error	36.160s	1.406ms	1	1	100.00
V2	key_error	kmac_key_error	4.350s	989.767us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	15.930s	10.196ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	9.190s	345.693us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	21.930s	1.871ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	10.840s	2.913ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	19.110s	910.981us	1	1	100.00
V2	stress_all	kmac_stress_all	13.548m	34.268ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.620s	133.433us	1	1	100.00
V2	alert_test	kmac_alert_test	1.490s	15.969us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.180s	106.440us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.180s	106.440us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.670s	27.285us	1	1	100.00
		kmac_csr_rw	1.670s	68.364us	1	1	100.00
		kmac_csr_aliasing	3.740s	257.048us	1	1	100.00
		kmac_same_csr_outstanding	1.980s	273.695us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.670s	27.285us	1	1	100.00
		kmac_csr_rw	1.670s	68.364us	1	1	100.00
		kmac_csr_aliasing	3.740s	257.048us	1	1	100.00
		kmac_same_csr_outstanding	1.980s	273.695us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.830s	35.561us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.830s	35.561us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.830s	35.561us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.830s	35.561us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.860s	27.196us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	45.610s	35.984ms	1	1	100.00
		kmac_tl_intg_err	2.810s	220.131us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.810s	220.131us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	19.110s	910.981us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	13.980s	501.265us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.055m	12.388ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.830s	35.561us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	45.610s	35.984ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	45.610s	35.984ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	45.610s	35.984ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	13.980s	501.265us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	19.110s	910.981us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	45.610s	35.984ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.488m	106.123ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	13.980s	501.265us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.539m	66.811ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.74020399794632519103430736596260880190355520944655473888592454107719123941421
      Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10196040164 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xae441000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10196040164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.108517310944345890789546401450570336551631909129407938950571690879153942167018
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  27195884 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  27195884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---